Deck 10: Sequential Circuits and Fault Detection Techniques

Question 1

Which of the following line is correct for detecting positive edge of a clock?

A)if (clk'event and clk = '0')
B)if (clk'event and clk = '1')
C)if (clk'event or clk = '0')
D)if (clk'event or clk = '1')

Answer 1

if (clk'event and clk = '1')

Question 2

A user doesn't want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.

Answer 2

True

Question 3

Sequential circuits are represented as

A)finite state machine
B)infinite state machine
C)finite synchronous circuit
D)infinite asynchronous circuit

Answer 3

finite state machine

Question 4

Sequential circuit includes

A)delays
B)feedback
C)delays and feedback from input to output
D)delays and feedback from output to input

Question 5

Which constitutes the test vectors in sequential circuits?

A)feedback variables
B)delay factors
C)test patterns
D)all input combinations

Question 6

Outputs are functions of

A)present state
B)previous state
C)next state
D)present and next state

Question 7

Which is the delay elements for clocked system?

A)and gates
B)or gates
C)flip-flops
D)multiplexers

Question 8

Which contributes to the necessary delay element?

A)flip-flops
B)circuit propagation elements
C)negative feedback path
D)shift registers

Question 9

In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be

A)a
B)0
C)1
D)b'

Question 10

Iterative test generation method suits for circuits with

A)no feedback loops
B)few feedback loops
C)more feedback loops
D)negative feedback loops only

Question 11

Which method is very time consuming?

A)d-algorithm
B)iterative test generation
C)pseudo exhaustive method
D)test generation pattern

Question 12

In this iterative test generation method, sequential logic is

A)used in the same pattern
B)converted to test logic
C)converted to combinational logic
D)converted to asynchronous logic

Question 13

For a NAND gate, struck-at 1 fault in second input line cannot be detected if

A)q is 1
B)q is 0
C)q changes from 1 to 0
D)q changes from 0 to 1

Question 14

Any condition that causes a processor to stall is called as______________  

A)hazard
B)page fault
C)system error
D)none of the mentioned

Question 15

In this technique, a simple fault manifests into multiple N faults.

Question 16

The contention for the usage of a hardware device is called____________

A)structural hazard
B)stalk
C)deadlock
D)none of the mentioned

Question 17

The situation wherein the data of operands are not available is called____________

A)data hazard
B)stock
C)deadlock
D)structural hazard

Question 18

The stalling of the processor due to the unavailability of the instructions is called as

A)control hazard
B)structural hazard
C)input hazard
D)none of the mentioned

Question 19

The time lost due to the branch instruction is often referred to as______________        

A)latency
B)delay
C)branch penalty
D)none of the mentioned

Question 20

____________method is used in centralized systems to perform out of order execution.

A)scorecard
B)score boarding
C)optimizing
D)redundancy

Question 21

The algorithm followed in most of the systems to perform out of order execution is______________    

A)tomasulo algorithm
B)score carding
C)reader-writer algorithm
D)none of the mentioned

Question 22

What are the typical values of tOE?

A)10 to 20 ns for bipolar
B)25 to 100 ns for nmos
C)12 to 50 ns for cmos
D)all of the mentioned

Question 23

Which of the following is not a type of memory?

A)ram
B)fprom
C)eeprom
D)rom

Question 24

The chip by which both the operation of read and write is performed______________    

A)ram
B)rom
C)prom
D)eprom

Question 25

RAM is also known as______________    

A)rwm
B)mbr
C)mar
D)rom