Deck 5: Flip-Flops and Related Devices

Question 1

Which of the following statements best describes an asynchronous digital system?

A) It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change.
B) It is easy to design and troubleshoot because the output state is independent of the inputs.
C) It is difficult to design and troubleshoot because the output cannot change states unless a clock input is synchronized to the SET and CLEAR inputs.
D) It is easy to design and troubleshoot because the exact times at which the output can change states is determined by a clock signal.

Answer 1

It is difficult to design and troubleshoot because the output can change states anytime one or more of the inputs change.

Question 2

Which of the following can result from a slow input signal transition?

A) Erratic triggering of flip- flops
B) Failure to produce an output signal
C) Oscillations may occur on the output of logic gates and inverters.
D) Both A and C
E) Both B and C

Answer 2

Both A and C

Question 3

A "D" flip- flop with a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?

A) CLK = NGT, D - 0
B) CLK = PGT, D = 1
C) CLK = NGT, D = 1
D) CLK = PGT, D = 0
E) Both A and C

Answer 3

CLK = PGT, D = 1

Question 4

Select the statement that best describes the two possible output states of a flip- flop.

A) The Q output is LOW and the output is LOW.
B) The Q output is LOW and the 11eea47d_d62b_67b7_97f4_05b8f844fe65_TB9839_11 output is HIGH.
C) The Q output is HIGH and the 11eea47d_d62b_67b7_97f4_05b8f844fe65_TB9839_11 output is LOW.
D) The Q output is HIGH and the 11eea47d_d62b_67b7_97f4_05b8f844fe65_TB9839_11 output is HIGH.
E) Both B and C

Question 5

Which of the following methods would be used to disable the PRESET (PRE) and CLEAR (CLR) inputs to a clocked flip- flop in a circuit application where they are NOT used?

A) Connect the and inputs to a HIGH logic level.
B) Connect the 11eea47d_ed02_e0d8_97f4_99d868dc8948_TB9839_11 and 11eea47e_0c84_858a_97f4_4f055cde406c_TB9839_11 inputs to a LOW logic level.
C) Connect the 11eea47d_ed02_e0d8_97f4_99d868dc8948_TB9839_11 input to a HIGH logic level and the 11eea47e_0c84_858a_97f4_4f055cde406c_TB9839_11to a LOW logic level.
D) Connect the 11eea47d_ed02_e0d8_97f4_99d868dc8948_TB9839_11input to a LOW logic level and the 11eea47e_0c84_858a_97f4_4f055cde406c_TB9839_11 input to a HIGH logic level.

Question 6

What type of multivibrator has no stable state?

A) Bistable
B) Astable
C) Monostable
D) Both A and C

Question 7

Which of the following is the most common use of flip- flops?

A) Switch debouncing
B) Pulse steering circuits
C) Combinatorial logic arrays
D) Storage registers

Question 8

A NAND latch has outputs of Q = 1 and = 0. What effect will applying a LOW to the CLEAR input have on the latch?

A) Q will go LOW and 11eea47e_3372_ccbb_97f4_47ddbec4d426_TB9839_11will go HIGH.
B) It will have no effect because a HIGH input is required to change NAND latch states.
C) Q will remain HIGH and 11eea47e_3372_ccbb_97f4_47ddbec4d426_TB9839_11 will remain LOW.
D) It will have no effect because the latch is already in the CLEAR state.

Question 9

A 1.5 MHZ clock signal is applied to an eight flip- flop binary counter. Which of the following indicates the proper MOD number, maximum number of counts, maximum count, and output frequency of the circuit?

A) MOD 128, 128 counts, 127 maximum count, and 23,437.5 Hz
B) MOD 512, 512 counts, 511 maximum count, and 2,929.69 Hz
C) MOD 256, 256 counts, 255 maximum count, and 5,859.38 Hz
D) MOD 256, 256 counts, 255 maximum count, and 11,718.75 Hz

Question 10

A primary difference between a clocked J- K flip- flop and a clocked S- C flip- flop is the J- K's ability to:

A) always reset to the CLEAR state when J = 1, K = 1, and a clock transition occurs.
B) remain in the CLEAR state when J = 1, K = 0, and a clock transition occurs.
C) toggle or change states when J = 1, K = 1, and a clock transition occurs.
D) always reset to the set state when J = 1, K = 1, and a clock transition occurs.

Question 11

You need to build a circuit to perform parallel data transfers from one set of registers to another. The interconnections between the registers must be held to a minimum. The best choice for the register FFs is the _____type.

A) latch
B) "D"
C) "J- K"
D) "S- C"

Question 12

Which statement best describes the operation of a NGT- triggered D flip- flop?

A) The Q output is always identical to the D input.
B) The Q output is always identical to the CLK input if the D input is HIGH.
C) The Q output is always identical to the D input when CLK makes a PGT.
D) The logic level at the D input is transferred to Q on NGT of CLK.

Question 13

Which of the following logic devices has only one stable state?

A) Monostable multivibrator
B) Astable multivibrator
C) J- K flip- flop
D) S- C flip- flop

Question 14

Which statement best describes the action of a NAND gate latch?

A) The SET and CLEAR inputs are normally HIGH with one or the other input pulsed LOW to change the outputs.
B) The SET input is normally LOW, the CLEAR input is normally HIGH, the SET input is pulsed HIGH to change the outputs.
C) The SET and CLEAR inputs are normally LOW with one or the other pulsed LOW to change the outputs.
D) The SET input is normally HIGH, the CLEAR input is normally LOW, the CLEAR input is pulsed LOW to change the outputs.

Question 15

What is the output frequency of a three- stage binary counter with an input clock frequency of 80 kHz?

A) 20 kHz
B) 10 kHz
C) 15 kHz
D) 5 kHz

Question 16

What factors determine the duration of the quasi- stable output pulse from a one- shot multivibrator?

A) An external resistor and capacitor
B) An external Schmitt- trigger circuit
C) The time between input trigger pulses
D) The duration of the input trigger pulse

Question 17

The asynchronous transfer of data between J- K storage registers can easily be accomplished using the:

A) PRESET and CLEAR inputs only.
B) Clock and the input J- K control signals.
C) Clock with the PRESET and CLEAR inputs.
D) J- K control signals only.

Question 18

A primary difference between a D flip- flop and the J- K and S- C flip- flops is the fact that:

A) a "D" flip- flop has one control input and no clock input.
B) a "D" flip- flop has only one control input and two clock inputs.
C) a "D" flip- flop has only one control input and one clock input.
D) a "D" flip- flop has two control inputs and no clock input.

Question 19

Forcing the SET input LOW on a NAND gate latch generates outputs of:

A) Q = 1 and = 1
B) Q = 0 and 11eea47e_619f_536c_97f4_ed5775673049_TB9839_11 = 1
C) Q = 0 and 11eea47e_619f_536c_97f4_ed5775673049_TB9839_11 = 0
D) Q = 1 and 11eea47e_619f_536c_97f4_ed5775673049_TB9839_11 = 0

Question 20

Which of the following circuit parameters would be most likely to limit the maximum operating frequency of an IC flip- flop?

A) Clock pulse HIGH and LOW time
B) Propagation delay time
C) Clock transition time
D) Set- up and hold time

Question 21

What is the output state of a MOD- 64 counter after 92 input pulses if the starting state is 000000?

A) 011110₂
B) 010110₂
C) 011100₂
D) 100100₂

Question 22

An internal_______________is primarily responsible for certain flip- flops to be designated as edge- triggered.

A) Edge- detection circuit
B) Pulse- steering circuit
C) NOR latch
D) NAND latch

Question 23

Which of the following logic devices is specifically designed to produce clean, fast- changing output signals?

A) NAND latch
B) NOR latch
C) Schmitt- trigger
D) J- K flip- flop

Question 24

Which of the following best describes the normal logical operation of a NOR gate latch?

A) Inactive SET and CLEAR inputs = 1, active SET input = 1, active CLEAR input = 0
B) Inactive SET and CLEAR inputs = 0, active SET or CLEAR inputs = 1
C) Inactive SET and CLEAR inputs = 0, active SET or CLEAR inputs = 0
D) Inactive SET and CLEAR inputs = 1, active SET input = 0, active CLEAR input = 1

Question 25

Which of the following statements regarding the small triangles in the IEEE/ANSI symbols for flip- flops is TRUE?

A) A triangle within the rectangle means edge- triggered and an external triangle indicates an active LOW input.
B) Triangles internal and external to the rectangle indicate active LOW inputs are required.
C) A triangle external to the rectangle means edge- triggered and internal triangles indicate active LOW inputs.
D) Internal triangles require active LOW inputs whereas external triangles indicate "Don't Care" conditions.

Question 26

Which of the following flip- flop timing parameters indicates the time it takes a Q output to respond to an input?

A) t_s, t_h
B) t_phl, t_plh
C) t_w(1), t_w(h)
D) f_max

Question 27

Select the statement that best describes the operation of retriggerable and non- retriggerable one- shot multivibrators.

A) A non- retriggerable one- shot may be retriggered in either its quasi- stable or stable state.
B) A retriggerable one- shot may be retriggered while in its quasi- stable state.
C) A non- retriggerable one- shot may be retriggered only while in its quasi- stable state.
D) A retriggerable one- shot must return to its stable state before it can be retriggered.

Question 28

Which of the following alternative logic gates would normally be used as a NAND latch equivalent representation?

A) active LOW input NOR gates
B) active HIGH input NOR gates
C) active LOW input OR gates
D) active HIGH input AND gates

Question 29

Asynchronous flip- flop preset and clear inputs generally:

A) cause the outputs to change states depending on the SR, JK, or similar controlling inputs.
B) clear the inputs so the flip- flop can start over.
C) cause the outputs to change states as soon as the input clock makes the desired transition.
D) act as manual overrides that cause the outputs to change states regardless of the inputs or clock transitions.

Question 30

The setup time of a clocked flip- flop is:

A) the minimum amount of time that an input must remain stable before an active clock transition.
B) the maximum amount of time that an output must remain stable after an active clock transition.
C) the minimum amount of time that an input must remain stable after an active clock transition.
D) the minimum amount of time that an output must remain stable before an active clock transition.

Question 31

What type of multivibrator produces a continuous pulse train?

A) Bistable
B) Astable
C) Monostable
D) all of the above

Question 32

How many shift pulses would be required to serially shift the contents of one six- stage register to another?

A) 8
B) 5
C) 6
D) 7

Question 33

The symbol for a flip flop has a small triangle - and no bubble - on its clock (CLK) input. The triangle indicates:

A) the FF is level active and can only change states when the CLOCK = 1.
B) the FF is edge- triggered and can only change states when the clock goes 0 to 1.
C) the FF is an active LOW device and can only change states when the CLOCK = 0.
D) the FF is edge- triggered and can only change states when the clock goes from 1 to 0.

Question 34

Which of the following best describes the characteristics of a MOD- 16 counter?

A) Eight possible counts, a minimum count of 7₁₀, and frequency division by a factor of sixteen
B) Sixteen possible counts, a maximum count of 15₁₀, and frequency division by a factor of eight
C) Eight possible counts, a maximum count of 7₁₀ and frequency division by a factor of eight
D) Sixteen possible counts, a maximum count of 15₁₀, and frequency division by a factor of sixteen

Question 35

A negative- edge- triggered J- K flip- flop is presently in the CLEAR state. Which of the following input conditions will cause it to change states?

A) CLK = NGT, J = O, and K = 1
B) CLK = NGT, J = 1, and K = 0
C) CLK = PGT, J = 1, and K = 0
D) CLK = PGT, J = O, and K = 1

Question 36

The difference between a D- latch and an edge- triggered D- type flip- flop is that the latch:

A) is controlled by the logic level at its ENABLE input rather than a CLK transition.
B) triggers on either the rising or falling edge of an ENABLE signal rather than the CLK input logic level.
C) always "latches" the Q output to the D input regardless of other inputs.
D) always "latches" the Q output to the complement of the D input regardless of other inputs.

Question 37

The new IEEE/ANSI symbols for latches and flip- flop use the letter "C" to denote:

A) any input that will cause the device to change states.
B) any input that controls when other inputs will have an effect on the output.
C) the normal Q output.
D) the SET and RESET inputs.

Question 38

As a general rule for stable flip- flop triggering, the clock pulse rise and fall times must be:

A) of no consequence as long as the levels are within the determinate range of values.
B) at a maximum value to enable the input control signals to stabilize.
C) very short.
D) very long.

Question 39

Determine the output frequency for a binary counter that contains twelve flip- flops with an input clock frequency of 20.48 MHz.

A) 30.24 kHz
B) 5 kHz
C) 15 kHz
D) 10.24 kHz

Question 40

The ABEL statement Q = (D & EN) !QBAR means that the output Q will be:

A) HIGH if D and EN variables are HIGH, or if is LOW.
B) LOW if D and EN variables are HIGH and 11eea47f_0626_ec9d_97f4_6f748b6f3806_TB9839_11 is LOW.
C) HIGH if D and EN variables are HIGH and 11eea47f_0626_ec9d_97f4_6f748b6f3806_TB9839_11 is LOW.
D) LOW if D and EN variables are HIGH, or if 11eea47f_0626_ec9d_97f4_6f748b6f3806_TB9839_11 is LOW.

Question 41

The combination of Q = 1 and = 0 defines the:

A) flip- flop clear state.
B) flip- flop set state.
C) flip- flop reset state.
D) Both B and C

Question 42

The preset and clear inputs to a J- K flip- flop are HIGH (1). Which of the following is TRUE?

A) The Q output is in an ambiguous state.
B) The Q output is immediately set to 1.
C) The flip- flop is free to respond to its J, K, and clock inputs.
D) The Q output is immediately cleared.

Question 43

Three flip- flops are wired together as a binary counter and the input clock frequency is 600 Hz. What is the output frequency of the highest order Q output?

A) 50 Hz
B) 120 Hz
C) 100 Hz
D) 60 Hz

Question 44

The MOD number of a counter:

A) indicates the number of possible counter output states.
B) indicates the value of the highest state.
C) indicates the value of the lowest state.
D) indicates sum of inputs.

Question 45

An astable multivibrator:

A) is a free running multivibrator.
B) uses RC circuits to determine operating frequency.
C) has no stable state.
D) All of the above

Question 46

Figure 5- 1 The clocked S- C flip- flop in Figure 5- 1 is synchronized by the CLK pulse when:

A) the clock pulse transitions from LOW to HIGH.
B) the clock pulse transitions either HIGH- LOW or LOW- HIGH.
C) the clock pulse remains a constant HIGH.
D) the clock pulse remains a constant LOW.
E) the clock pulse transitions from HIGH to LOW.

Question 47

A D- type latch is able to change states and "follow" the D input regardless of the level of the ENABLE input.

Question 48

The usual stable state for one- shot is: Q = 1, Q = 0.

Question 49

A flip- flop is in the HIGH state when Q = 1.

Question 50

Generally, a flip- flop's hold- time is short enough to allow its output to be determined by the logic levels present at its synchronous control inputs just prior to the active clock transition.

Question 51

The Q output of a flip- flop is normally HIGH when the device is in the "CLEAR" or "RESET" state.

Question 52

74xxx standard logic chips are found in the megafunction library of the Quartus II development software.

Question 53

Parallel data transfers between two different sets of registers requires more than one shift pulse.

Question 54

A small triangle at the CLK input on a standard flip- flop symbol indicates that any change in the output is triggered by a clock transition.

Question 55

The setup time (t_s) of a flip- flop indicates the length of time a control input signal must be maintained at the proper level during active CLK transition time.

Question 56

An open or "floating" input on a flip- flop may pick up enough noise to cause the device to change states.

Question 57

A flip- flop is always SET by the positive- going transition that occurs when power is first applied.

Question 58

A flip- flop is a discrete electronic component.

Question 59

Flip- flops are integral to all electronic data transfer and memory systems.

Question 60

In HI- Z mode, data from the bus cannot be loaded to or retrieved from a D flip- flop.

Question 61

Due to very low current consumption by digital IC inputs, a pull- up resistor can provide a logic high with an open switch.

Question 62

Synchronous flip- flops require a clock input to change output states.

Question 63

All flip- flops hold the last logic level entered indefinitely.

Question 64

Flip- flops can be used as sequencing components.

Question 65

A one- shot has a stable output state that is essentially interrupted by the trigger input. Once interrupted, the output goes to the opposite state for a specific amount of time.

Question 66

LPMs are found in the megafunction library of Altera's Quartus II software.

Question 67

Retriggerable one- shots tend to reduce the HIGH (quasi- stable) output time upon successive triggers.

Question 68

A_____input to a S- R flip- flop results in an output state of Q = 1, Q = 0.

Question 69

In _____circuits, the outputs of logic circuits can change state independently of a clock (CLK) input.

Question 70

A clock transition from a LOW (0) to a HIGH (1) is called a _____ transition.

Question 71

An_____input is activated by a signal transition rather than a logic level.

Question 72

When operated in its_____mode, a FF changes states with each clock pulse.

Question 73

A flip- flop is also referred to as a_____multivibrator.

Question 74

A(n) _____ input requires a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

Question 75

A(n)_____ input does not require a clock (CLK) or enable (EN) signal to affect the output of a flip- flop.

Question 76

The three libraries in Altara's Quartus II development system software are named_____ ,_____ and_____ .

Question 77

Mechanical switches are susceptible to_____, which can be eliminated by using a NAND gate latch.

Question 78

A clock makes a _____transition when it switches from a zero to a one.

Question 79

_____flip- flop inputs override all other inputs.

Question 80

A_____accepts slow- changing input signals and generates clean, fast- transition output signals.