Deck 8: Integrated-Circuit Logic Families

Question 1

The DC high- state noise margin is the difference between the:

A) highest possible HIGH output and the minimum input voltage required for a HIGH.
B) lowest possible HIGH output and the maximum input voltage required for a HIGH.
C) highest possible HIGH output and the maximum input voltage required for a HIGH.
D) lowest possible HIGH output and the minimum input voltage required for a HIGH.

Answer 1

lowest possible HIGH output and the minimum input voltage required for a HIGH.

Question 2

Suppose the data sheet for a standard TTL four NOR gate IC lists values of: I_cch = 6 ma, I_ccl = 16 ma, and V_cc = 5 v. What is the average power dissipated by each gate?

A) 50 mw
B) 55 mw
C) 13.75 mw
D) 12.50 mw

Answer 2

13.75 mw

Question 3

Which of the following is a disadvantage of a totem- pole output?

A) When switching from HIGH to LOW, Q₄ is changing from saturation to cutoff. This transition takes longer than Q₃'s transition so for a short period a surge of current is drawn from V_cc.
B) When switching LOW to HIGH, Q₃ is changing from saturation to cutoff. This transition takes longer than Q₄'s transition so for a short period a surge current is drawn from V_cc.
C) When switching from LOW to HIGH, Q₄ is changing from saturation to cutoff. This transition takes longer than Q₃'s transition so for a short period a surge of current is drawn from V_cc.
D) Both A and C

Answer 3

When switching from LOW to HIGH, Q₄ is changing from saturation to cutoff. This transition takes longer than Q₃'s transition so for a short period a surge of current is drawn from V_cc.

Question 4

For conduction, a P- channel MOSFET switch would require a____ V_DD and a ____ V_GS.

A) negative, positive
B) positive, positive
C) negative, negative
D) positive, negative

Question 5

When CMOS logic circuits are driving TTL logic circuits, any current mismatch problems can usually be overcome by the addition of:

A) a CMOS noninverting bilateral switch between the stages.
B) a TTL tri- state noninverting buffer between the stages.
C) a TTL tri- state inverting buffer between the stages.
D) a CMOS inverting bilateral switch between the stages.

Question 6

Any input voltage ____is invalid for a TTL logic gate.

A) less than 0.8 V
B) greater than 2.0 V
C) between 0.8 V and 2.0 V

Question 7

A TTL data sheet lists the following values for the 74LS190 synchronous counter: I_OH(max) = - 0.4 mA, I_OL(max) = 8 mA, I_IH(max) = 60 µA, and I_IL(max) = - 1.2 mA. Determine the same series

A) 2
B) 4
C) 6
D) 5

Question 8

The term "wired AND" refers to:

A) wiring multiple outputs to an external AND gate to perform the desired AND function.
B) wiring multiple outputs to a common ground.
C) wiring multiple outputs to a common point. The common tie point performs the AND function.
D) wiring multiple outputs to an active LOW input OR gate to perform the AND function.

Question 9

A bipolar TTL logic family that was developed to increase switching speed by preventing transistor saturation is:

A) emitter- coupled logic (ECL).
B) transistor- transistor logic (TTL).
C) current- mode logic (CML).
D) Both A and C

Question 10

The MOS logic circuit fan- out is generally_____ than TTL fan- outs and the power drain is usually____ than for TTL.

A) greater, less
B) less, less
C) less, greater
D) greater, greater

Question 11

The TTL IC chip parameter that defines the input voltage level required for a logical "1" at an input is:

A) ^VOH(min)^{.
B) V}IL(max)^{.
C) V}OL(max)^{.
D) V}IH(min)^.

Question 12

The voltage measured at an unused TTL input typically falls in the range of:

A) 0.8 to 5 V
B) 1.4 to 1.8 V
C) 0 to 5 V
D) 0 to 1.8 V

Question 13

Which of the following MOST accurately lists the advantages of MOS ICs over TTL ICs?

A) Occupy more space, are less expensive to manufacture, are bipolar devices, and normally do not use IC resistor elements
B) Occupy less space, operate faster, are less expensive to manufacture, and consume less power
C) Occupy less space, operate faster, and are easier to fabricate
D) Occupy less space, require fewer external connections, are unipolar devices, and normally do not use IC resistor elements

Question 14

The V_OH(min) rating of a TTL gate is lower than the V_IH(min) rating of a CMOS gate. Which of the following is commonly used to overcome this problem?

A) Adding a fixed voltage divider bias resistive network at the output of the TTL device
B) Adding an external pull- up resistor to V_cc
C) Adding an external pull- down resistor to ground
D) Avoiding this condition and only using TTL to drive TTL

Question 15

The two primary advantages to using a totem- pole output circuit in TTL logic devices are:

A) increased power dissipation and slow rise- time waveforms at TTL outputs with capacitive loads.
B) reduced power dissipation and fast rise- time waveforms at TTL outputs with capacitive loads.
C) increased power dissipation and fast rise- time waveforms at TTL outputs with capacitive loads.
D) reduced power dissipation and slow rise- time waveforms at TTL outputs with capacitive loads.

Question 16

The IEEE/ANSI notation of an internal underlined diamond denotes:

A) quadrature amplifiers.
B) tri- state buffers.
C) open- collector outputs.
D) totem- pole outputs.

Question 17

An identification number of 74HCT would identify the series as a:

A) high- speed CMOS that can be directly driven by TTL.
B) low- speed CMOS that can be directly driven by TTL.
C) low- speed TTL that can directly driven by CMOS.
D) high- speed TTL that can be directly driven by CMOS.

Question 18

As a general rule, the lower the value of the speed- power product, the better the device because of its:

A) short propagation delay and low power consumption.
B) long propagation delay and high power consumption.

Question 19

An IC is rated I_OH(max) = 600 µA and I_OL(max) = 60 mA. Express the IC's fan- out in terms of standard TTL unit loads (UL).

A) HIGH state = 8 UL, LOW state = 10 UL
B) HIGH state = 12 UL, LOW state = 18 UL
C) HIGH state = 2.5 UL, LOW state = 1.5 UL
D) HIGH state = 15 UL, LOW state = 37.5 UL

Question 20

When totem pole outputs are tied together:

A) nothing unusual happens.
B) a wired- AND condition safely exists.
C) the HIGH state prevails.
D) eventual, if not immediate, damage may occur.

Question 21

Any unused input for a NOR gate should be tied to:

A) another unused input.
B) ground.
C) V_cc via a 1 resistor.
D) Either B or C

Question 22

Which of the following MOSFET families has the advantage of higher speed and much lower power dissipation (as compared to the others)?

A) CMOS
B) N- MOS
C) MOSFET
D) P- MOS

Question 23

The CMOS bilateral switch is:

A) a logic device similar to its ECL counterpart with input and output terminals that are not interchangeable.
B) a logic device similar to its TTL counterpart with input and output terminals that are not interchangeable.
C) a logic device with a control input that makes it act like a SPST switch, and interchangeable input and output terminals.
D) a logic device with a control input that makes it act like a SPST switch, and non- interchangeable input and output terminals.

Question 24

Determine the output state for a TTL NOR gate that has all of its inputs floating.

A) HIGH
B) LOW
C) Indeterminate

Question 25

The term that describes the maximum number of standard logic inputs that an IC output can drive reliably is:

A) power requirements.
B) noise immunity.
C) speed- power product.
D) fan- out

Question 26

The voltages applied to the input of any standard TTL series IC must never exceed +5.5 v because:

A) a greater voltage applied to a collector can cause a reverse breakdown of the B- C junction.
B) a greater voltage applied to a base input can cause reverse breakdown of the E- B junction Of Q₁.
C) a greater voltage applied to an emitter input can cause reverse breakdown of the E- B junction Of Q₁.
D) a greater voltage applied to a base can cause a reverse breakdown of the B- C junction.

Question 27

The Quartus II software has two tools that are used to estimate power consumption. The PowerPlay Power Analyzer is used ______ .

A) only for minimum clocking speeds
B) later in the design process
C) earlier in the design process
D) to get an exact power consumption value

Question 28

When open collector outputs are wired together, the______ function is performed.

A) OR
B) AND
C) INVERSION
D) NAND

Question 29

In digital circuits, one MOSFET (Q₁₎ is usually used as the:

A) input MOSFET for other MOSFETs in the circuit.
B) load resistor for the switching MOSFET.
C) buffer MOSFET for the other MOSFETs.
D) None of the above

Question 30

A "floating" TTL input is an:

A) unused input that is tied to ground.
B) unused input that is not connected.
C) unused input that is tied to used inputs.
D) unused input that is tied to Vcc through a 1- k? resistor.

Question 31

An IC logic gate draws 1.8 mA when its output is HIGH and 3.8 mA when its output is LOW. Assume a 50% duty cycle and calculate the average I_cc current drain.

A) 3.8 mA
B) 2.8 mA
C) 2.0 mA
D) 1.8 mA

Question 32

Assume a V_cc of 5 V for the preceding question and determine the average power dissipation, ^PD(ave)^.

A) 9 mW
B) 14 mW
C) 19 mW
D) 10 mW

Question 33

The logic devices that are most commonly used to drive a wired- AND circuit are:

A) open- collector TTL devices.
B) standard TTL output totem- pole devices.
C) CMOS devices.
D) MOS devices.

Question 34

Which of the following IC logic families are most susceptible to static discharge?

A) MOS
B) ECL
C) TTL
D) CML

Question 35

The main difference between an SN7402 and an SN5402 would be:

A) the SN7402 contains NOR gates where the SN5402 contains NAND gates.
B) the SN5402 contains NOR gates where the SN7402 contains NAND gates.
C) the SN5402 is able to operate over a wider range of temperatures and power supply voltages.
D) the SN7402 is able to operate over a wider range of temperatures and power supply voltages.

Question 36

Generally, an increase in load capacitance to a MOS logic output results in:

A) an increase in switching time.
B) a decrease in fan- out capability.
C) a decrease in switching time.
D) Both A and B

Question 37

Two important points concerning emitter- coupled logic are:

A) the output voltage levels are the same as the input logic levels and the two outputs are in phase with each other.
B) the output voltage levels are not the same as the input logic levels and the two outputs are complements of each other.
C) the output voltage levels are not the same as the input logic levels and the two outputs are in phase with each other.
D) the two output voltage levels are the same as the input logic levels and the two outputs are complements of each other.

Question 38

The inherent signal delays produced by a logic device are identified as:

A)^IOH ^{and I}OL^.
B)VIL(max) ^{and V}IH(min)<sup>.

C)V</sup>OH(min) ^{and V}OL(max)^{.
D) t}PLH ^{and t}PHL^.

Question 39

A logic device has the following specifications: V_OL(max) = 0.5 V, V_IL(max) = 0.9 V, V_OH(min) =2.6V,and V_IH(min)=2.1V.Determine the Low-state dc noise margin for the device .

A) 0.9 V
B) 0.5 V
C) 2.1V
D) 0.4 V

Question 40

Exceeding the fan- out capability of a specific TTL series can cause:

A) I_OL and I_OH to exceed their maximum values, forcing V_OL to exceed its maximum rated value and V_OH to fall below its minimum rated value.
B) I_OL and I_OH to exceed their maximum values, forcing V_OL to fall below its minimum rated value and V_OH to exceed its maximum rated value.

Question 41

The IC chip parameter that describes the output current generated in the logical "O" state under specified load conditions is:

A) I_IL
B) I_IH
C) I_OH
D) I_OL

Question 42

The measure of a logic circuit's ability to withstand random noise on its inputs without causing spurious changes in the output voltage is called:

A) speed- power product.
B) noise immunity.
C) fan- out.
D) Both A and C

Question 43

Tri- state buffers are commonly used to:

A) perform the exclusive NOR operation.
B) perform the AND operation.
C) simultaneously connect multiple signals to a single bus line.
D) sequentially connect multiple signals to a single bus line.

Question 44

Examination of the input and output signals of an IC inverter reveals a delay from the time the input goes LOW until the output goes HIGH. The delay between these two signals should be measured at the amplitude points and be labeled .

A) 50 percent, t_PHL
B) 50 percent, t_PLH
C) 100 percent, t_PLH
D) 100 percent, t_PHL

Question 45

The term "pin compatible" means:

A) pin configurations are the same.
B) the pins fit together.
C) logic functions performed are the same.
D) all pins are the same size.

Question 46

A single rating that is commonly used to compare the propagation delay and power dissipation characteristics of various circuits is the:

A) noise immunity factor.
B) power- delay rating.
C) speed- power product.
D) fan- out.

Question 47

The word interface, as applied to digital electronics, usually refers to:

A) a circuit connected between the driver and load to condition a signal so that it is compatible with the load.
B) any gate that is a TTL operational amplifier designed to condition signals between N- MOS transistors.
C) any TTL circuit that is an input buffer stage.
D) a conditioning circuit connected between a standard TTL NAND gate and a standard TTL OR gate.

Question 48

The highest speed version for the Cyclone II chip is the dash ______.

A) six
B) seven
C) five
D) eight

Question 49

If a situation calls for a TTL circuit to drive a CMOS circuit, you should:

A) do nothing special. A TTL should be able to drive CMOS IC without any problems.
B) ensure that the electrical parameters for both ICs are compatible.
C) ensure that the two ICs are pin compatible with each other.
D) ensure that both chips have the same fan out.

Question 50

For standard TTL, a LOW- level input voltage can be:

A) 0 - 0.8 V
B) 0 - 2 V
C) 0 - 5 V
D) 2 - 5 V

Question 51

Tri- state devices with input and output enable controls simplify interfacing tasks by allowing the user to:

A) connect only inputs from different devices to the same bus.
B) connect a mix of both inputs and outputs from different devices to the same bus.
C) connect only outputs from different devices to the same bus.

Question 52

In the high- impedance state, tri- state devices:

A) allow input data to pass through the device.
B) have their enables electrically isolated from other circuits.
C) have their outputs electrically isolated from other circuits.
D) have their inputs electrically isolated from other circuits.

Question 53

When interfacing components in a circuit, "transmission line" issues can be avoided if the components are placed no more than ______from each other.

A) 1.51 feet
B) 9 inches
C) 4 feet
D) 4 inches

Question 54

The primary advantage of ECL over TTL is that ECL circuits have:

A) very short propagation delay times.
B) low noise margins.
C) constant current drain.
D) Both A and C

Question 55

A device used to compare an analog voltage to a reference value, for the purpose of generating a digital signal is called a(n):

A) analog limiter.
B) step inverter.
C) digital converter.
D) comparator.

Question 56

If not connected to a ground or logic high signal, TTL inputs:

A) are considered logic high.
B) are logic low.
C) automatically go to Hi- Z mode.
D) are invalid.

Question 57

The chief advantage of MOS technology is that:

A) it has low power dissipation.
B) it is inexpensive to produce.
C) it has very low loading effects.
D) All of these are important advantages.

Question 58

The chief disadvantage of MOS technology is:

A) its high cost.
B) it is subject to static electricity damage.
C) its high current consumption.
D) it has fewer gates per packages than TTL.

Question 59

If a logic pulser indicates a constant low at a particular node:

A) the node is grounded.
B) the node is pulsing.
C) the node is open.
D) the node is high.

Question 60

A shorted input to ground or output to ground can be detected using:

A) a current tracer.
B) a pulser.
C) a logic probe.
D) Both A and B

Question 61

-Refer to Table 8- 1. Which of the series listed would be best suited for operating in a portable battery powered circuit at 100 MHz?

A) 74S
B) 74F
C) 74AS
D) 74ALS

Question 62

-Refer to Table 8- 1. Which TTL series has the lowest speed- power product and what are the values of t_D and P_D that produce the product?

A) 74F
B) 74ALS
C) 74S
D) 74AS

Question 63

-Refer to Table 8- 1. Which series has the largest dc noise margin (V_NL)?

A) 74S/74LS/74AS/74F
B) 74/74LS/74ALS
C) 74/74AS/74F
D) 74/74ALS

Question 64

-Refer to Table 8- 1. Which series is capable of driving the fewest device inputs of the same series?

A) 74S/74LS
B) 74F
C) 74AS
D) 74

Question 65

"Ringing" is a word that refers to the overshoot, undershoot, and damped oscillations that appear on many pulse signals.

Question 66

Open- collector circuits are especially well suited for high speed switching circuits.

Question 67

The principal advantage of MOS circuits over TTL circuits is their fast operating speed.

Question 68

TTL NOR and NAND gates use multiple- emitter transistors on their inputs.

Question 69

The dc noise margins calculated using the proper values from a standard TTL data sheet are the worst- case margins. The typical dc noise margins are usually somewhat higher.

Question 70

The value of V_CCIO for the Cyclone II chips is determined by the desired output logic level.

Question 71

A certain TTL series has a fan- out of 20. This means the series is capable of driving a total of 20 input devices of any series.

Question 72

Power supply decoupling consists of radio- frequency capacitors connected from V_cc to ground to "short" high- frequency voltage spikes to ground.

Question 73

A major drawback in using ECL logic circuits in conjunction with TTL and MOS circuits is its negative supply voltages and logic levels.

Question 74

P- MOS and N- MOS circuits are usually identical with the exception of the voltage polarities.

Question 75

Devices using single- ended interfaces have better noise immunity than those using differential signaling.

Question 76

3.3 V devices should never be subjected to 5.0 V.

Question 77

Most common digital integrated circuits can easily be used to drive high- current loads.

Question 78

Integrated circuits are best suited for information processing applications.

Question 79

TTL and ECL families use FET transistor technology.

Question 80

CMOS logic families use bipolar transistor technologies.