Deck 11: Interfacing With the Analog World

Question 1

If a DAC has an open input, it would most probably fail the:

A) applied quadrature test.
B) t_PHL- t_PLH test.
C) staircase test.
D) Ground- V_cc test.

Answer 1

staircase test.

Question 2

What will happen if the input analog voltage (V_a) is greater than a digital- ramp ADC's full- scale (V_ax) value?

A) The counter will count up to its maximum value causing V_ax to reach its full- scale output. All operations will then cease until V_ax decreases below V_ax.
B) The comparator will detect that V_a is larger than the V_ax full- scale output and all operations will cease until V_a decreases below V_ax full- scale.
C) The counter will repetitively count up from zero to maximum producing a continuously repetitive staircase waveform at V_ax.
D) The comparator will detect that V_a is beyond the range of V_ax and will keep the ADC's output at zero until V_a is decreased below V_ax full- scale.

Answer 2

The counter will repetitively count up from zero to maximum producing a continuously repetitive staircase waveform at V_ax.

Question 3

A digital- to- analog converter has a step size of 0.25 V and a full- scale output of 7.75 V. Determine the percent of resolution and the number of input binary bits.

A) 3.23%, 5 bits
B) 3.23%, 4 bits
C) 31%, 4 bits
D) 31%, 5 bits

Answer 3

3.23%, 5 bits

Question 4

The output of a basic four- bit input digital- to- analog converter would be capable of outputting:

A) 32 different values of voltage or current that are proportional to the input binary number.
B) 16 different values of voltage or current that are not proportional to the input binary number.
C) 16 different values of voltage or current that are proportional to the input binary number.
D) 32 different values of voltage or current that are not proportional to the input binary number.

Question 5

What is the greatest output current value from an 8- bit input DAC that has an output of 4.5 mA when the input binary number is 01101010₂?

A) 8.41 mA
B) 10.83 mA
C) 9.73 mA
D) 4.37 mA

Question 6

Select the statement that best describes the input resistor values for a simple DAC using an op- amp as a summing amplifier.

A) They are binarily weighted with the LSB resistor having the largest value and the MSB having a value equal to the feedback resistor.
B) They are binarily weighted with the LSB resistor having a value equal to the feedback resistor and the MSB having the highest value.
C) Starting with the MSB resistor, the values decrease by a factor of 4 to the LSB resistor.
D) Starting with the LSB resistor, the values increase by a factor of 4 to the MSB resistor.

Question 7

A technician is wiring a circuit that requires a DAC. Two DAC's are available with the proper full- scale output. His requirements are for small resolution values and precision in the analog output. Generally, the DAC with the step size and the percent of resolution should be selected.

A) largest, smallest
B) largest, largest
C) smallest, largest
D) smallest, smallest

Question 8

Refer to the preceding problem. The DAC that is selected would be required to have:

A) the same number of input binary bits as the rejected DAC.
B) fewer input binary bits than the rejected DAC.
C) a greater number of input binary bits than the rejected DAC.
D) greater resolution per step than the rejected DAC. Resolution and the number of input binary bits have no bearing on each other in this instance.

Question 9

An actuator is usually a device that:

A) converts a physical variable to an electrical variable.
B) converts analog data to meaningful digital data.
C) stores digital data and then processes that data according to a set of specified instructions.
D) controls a physical variable.

Question 10

One purpose of the comparator in a digital- ramp ADC is to:

A) enable the control unit as long as V_ax is less than V_a.
B) staircase the input analog for comparison with V_ax.
C) enable the control unit as long as V_ax is greater than V_a.
D) generate clock pulses to up- count the binary counter.

Question 11

A certain digital- to- analog converter has a proportionality factor (K) of 0.6 V. Determine the input binary number if the output voltage is 5.4 V.

A) 1100₂
B) 1010₂
C) 1011₂
D) 1001₂

Question 12

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 mA. How many possible output current steps can this DAC produce?

A) 999₁₀
B) 4096₁₀
C) 4095₁₀
D) 1000₁₀

Question 13

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 ma. What is the resolution of the DAC?

A) 12 µA
B) 50 µA
C) 11 µA
D) 49 µA

Question 14

Suppose that a 3- digit BCD digital- to- analog converter has a full- scale output of 49.95 mA. What is the percentage resolution of the DAC?

A) 0.02%
B) 0.20%
C) 0.10%
D) 0.01%

Question 15

Suppose that a 3- digit BCD digital- to- analog converter has a BCD input of 0100 1001 0111. Assuming the converter has a full- scale output of 49.95 mA, the output current will be:

A) 1.17 mA
B) 11.17 mA
C) 24.85 mA
D) 49.84 mA

Question 16

The two basic methods to test a DAC's operation consist of:

A) a basic IC chip test to determine if: (1) the V_cc and (2) ground inputs are functioning normally.
B) a static accuracy test and a staircase test.
C) an analog- to- digital conversion test to determine DAC accuracy and a digital- to- analog conversion test.
D) a drift test to determine if the DAC output falls within the specified ranges and a quadrature test.

Question 17

Which of the following is a characteristic of a pipelined ADC employing flash ADCs in the subranging stages?

A) It has high resolution.
B) It is relatively inexpensive.
C) It is fast.
D) all of the above

Question 18

The output error of an ADC is obtained by:

A) subtracting the quantization error from the full- scale error.
B) adding the full- scale error to the quantization error.
C) subtracting the full- scale error from the quantization error.

Question 19

The most likely ADC architecture for the majority of complex data acquisition systems is:

A) successive approximation.
B) pipelined.
C) sigma/delta.
D) none of the above.

Question 20

The output voltage or current of a transducer would normally be the input of a(n):

A) DAC.
B) ADC.
C) Actuator.
D) Digital system.

Question 21

When comparing the conversions from digital- to- analog and analog- to- digital, the A/D conversion is generally:

A) less complicated but more time consuming than the D/A conversion.
B) more complicated and more time consuming than the D/A conversion.
C) less complicated and less time consuming than the D/A conversion.
D) more complicated but less time consuming than the D/A conversion.

Question 22

Digital quantities have values that are specified as 1 or 0, HIGH or LOW, etc. The voltage values associated with these digital quantities fall within specified limits. On the other hand, analog values for physical process control may be any value over a wide range of values, with each different value having a different meaning. As a result:

A) digital computers that monitor or control analog physical values must have an accurate means of transforming analog data to meaningful digital data and vice- versa.
B) digital computers are unable to monitor or control physical analog operations with any degree of accuracy or certainty.
C) digital computers have the capability to monitor only those analog physical operations that fall within the specified ranges of digital HIGH and LOW voltage levels.
D) digital computers are unable to monitor analog physical values regardless of the interfacing techniques used to make the two systems compatible.

Question 23

A DAC is monotonic if its output:

A) increases and decreases as the binary input increases from one input to the next.
B) decreases as the binary input increases from one value to the next.
C) increases as the binary input increases from one value to the next.
D) increases and decreases as the binary input decreases from one input to the next.

Question 24

The most likely ADC architecture for a spectrum analyzer is:

A) pipelined.
B) sigma/delta.
C) successive approximation.
D) none of the above.

Question 25

The resolution or step size of a 4- bit, or any other, digital- to- analog converter may be defined as:

A) the value of the K proportionality factor.
B) the difference in the analog value from the smallest binary input and the largest binary input (in this example 0000₂- 1111₂₎ or as the weight of the MSB.
C) the difference in the analog value from the binary input 0000₂- 0001₂, or as the weight of the LSB.
D) Both A and C

Question 26

A transducer is a device that:

A) converts a physical variable to an electrical variable.
B) controls a physical variable.
C) converts analog data to meaningful digital data.
D) stores digital data and then processes that data according to a set of specified instructions.

Question 27

Suppose that a certain 8- bit DAC has a full- scale output of 12 V and a full- scale error of 0.5%. What is the range of possible outputs for an input of 10110101₂?

A) 7.63 V - 8.51 V
B) 8.46 V - 8.58 V
C) 7.47 V - 7.59 V
D) 8.47 V - 8.59 V

Question 28

A digital- to- analog converter (DAC):

A) converts the analog input from a transducer or some other device to a representative digital input for a computer or some other digital device.
B) converts the digital output of a computer to a corresponding analog representation, usually voltage or current.
C) monitors the digital representation of an analog value during the computer's program execution.
D) converters a digital value to a representative physical analog value such as pressure or temperature.

Question 29

The quantization error in an analog- to- digital converter can be reduced by:

A) decreasing the number of bits in the counter and DAC.
B) increasing the number of bits in the counter and DAC.
C) decreasing the number of bits in the counter and increasing the number of bits in the DAC.
D) increasing the number of bits in the counter and decreasing the number of bits in the DAC.

Question 30

Two ways to determine the output of a BCD digital- to- analog converter are to:

A) divide the full scale output value by the BCD weights of all bits that are 1s, or determine the decimal value for each BCD code group and multiply that value by the step size.
B) sum the straight binary weights of the input bits that are 1s, or determine the decimal value of the inputs and multiply this value by the step size.
C) sum the BCD weights of all bits that are 1s, or add the decimal value for each BCD code group and multiply that value by the step size.
D) divide the straight binary weights of the input bits that are 1s by the full scale value, or determine the decimal value of the inputs and multiply that value by the step size.

Question 31

The main advantages of the successive- approximation ADC over the digital- ramp ADC is its:

A) shorter conversion time.
B) more complex circuitry.
C) longer conversion time.
D) less complex circuitry.

Question 32

Sample- and- hold circuits in ADCs are designed to:

A) sample and hold the output of the binary counter during the conversion process.
B) stabilize the input analog signal during the conversion process.
C) sample- and- hold the DAC staircase waveform during the conversion process.
D) stabilize the comparator's threshold voltage (V_T) during the conversion process.

Question 33

If you were designing a computer data acquisition system that required the use of analog- to- digital converters when analog data are changing at a fast rate, you would most likely select an SAC A/D converter over a digital- ramp A/D because:

A) the SAC will enable the computer to acquire more data values in a given period of time.
B) the SAC is less complicated than its digital- ramp counterpart.

Question 34

Two principal advantages of the Dual- Slope ADC are its:

A) low sensitivity to noise and high speed.
B) high sensitivity to noise and low cost.
C) low sensitivity to noise and low cost.
D) high speed and low cost.

Question 35

The process of a computer generating a START pulse, examining EOC, and loading ADC data into memory is controlled by:

A) the clock pulse input to the ADC.
B) the data acquisition program.
C) the magnitude of V_AX.
D) the magnitude of V_A.

Question 36

Which of the following A/D converters is the highest- speed ADC available?

A) Flash
B) Successive- approximation
C) Digital- ramp

Question 37

A Sample and Hold circuit's acquisition time is dependent upon:

A) voltage V_o.
B) the output impedance of A₁.
C) the digital control circuitry.
D) the value of C_h.

Question 38

The three types of ADCs that do not use a DAC as part of the conversion process are:

A) flash ADC, digital- ramp ADC, and dual- slope ADC.
B) successive- approximation ADC, digital- ramp ADC, and dual- slope ADC.
C) flash ADC, voltage- to- frequency ADC, and dual- slope ADC.
D) digital- ramp ADC, tracking ADC, and dual- slope ADC.

Question 39

A major application for Digital Signal Processing is in filtering and conditioning:

A) binary numbers.
B) digital signals.
C) analog signals.
D) square waves.

Question 40

The sampling frequency for a 10 KHz input signal should be samples per second.

A) at least 10,000
B) at most 10,000
C) at least 20,000
D) at most 5,000

Question 41

Signal aliasing results in:

A) the sampled signal representing the original input signal.
B) the sampled signal having a frequency that is half the original input signal.
C) the sampled signal having a frequency that is twice the original input signal.
D) the sampled signal having a frequency that is equal to the difference between the sample frequency and the incoming signal frequency.

Question 42

A particular tachometer displays engine RPMs from zero to 10,000. If the ADC accepts voltage levels from zero to five volts, in order to achieve full- scale representations from the tachometer, what should the output voltage be at 8500 RPM?

A) 5 volts
B) 4.8 volts
C) 3.2 volts
D) 4.25 volts

Question 43

A given 4- bit digital to analog converter has a reference voltage of 15 volts and a binary input of 0101. What is the proportionality factor?

A) 15 V
B) 1.5 V
C) 1 V
D) 5 V

Question 44

An A/D converter has a binary input of 0010 and an analog output of 20 mV. What is the resolution?

A) 100 mV
B) 20 mV
C) 1 mV
D) 10 mV

Question 45

D/A converters output ideal voltages. The actual output will vary from the ideal output for several different reasons. Which of the following is NOT a factor in determining output voltage accuracy?

A) The precision of the resistor used in the summing amplifier output
B) The number of logic input bits
C) The precision of the input voltage level
D) The precision of the resistors used in the summing amplifier input

Question 46

Which of the following is NOT a typical manufacturer's specification for D/A converters?

A) settling time
B) offset error
C) reference voltage
D) monocity

Question 47

Successive approximation analog/digital counters have:

A) shorter conversion time than digital ramp ADCs.
B) increased resolution than DR ADL.
C) weighted value type appropriation circuitry.
D) Both A and C

Question 48

Signal aliasing occurs when sampling frequency is 10× the highest input signal frequency or higher.

Question 49

In data acquisition systems, a single analog- to- digital converter (ADC) may be shared by several analog sources.

Question 50

Simply stated, for an N- bit DAC the number of different levels will equal 2ⁿ, and the number of steps will equal 2ⁿ - 1.

Question 51

The output voltage or current of a digital- to- analog converter is truly an analog signal.

Question 52

A primary advantage of R/2R ladder DACs over binary weighted resistor DACs is the R/2R device only uses two different resistor values.

Question 53

The static accuracy test is the normal procedure used to test the monotonicity of a DAC.

Question 54

Flash A/D converters depend on an input clock pulse to perform each conversion.

Question 55

The full- scale output for an 8- bit digital- to- analog converter would be reached when the binary input number equals 128₁₀.

Question 56

Resolution in the analog output of a DAC is primarily dependent on the number of input binary bits.

Question 57

If the feedback resistor (R_f) in a summing op- amp is increased by a factor of four, each input weight will be decreased by a factor of four.

Question 58

Generally speaking, DACs with current outputs have a shorter settling time than those with voltage outputs.

Question 59

Integrated ADCs can only have one input signal.

Question 60

Sample and Hold acquisition time depends on the value of C_h.

Question 61

Digital voltmeters need an ADC with a very fast conversion time.

Question 62

DSP works only on digital signals.

Question 63

The digital representation of the process variable is transmitted from the ADC to the digital computer.

Question 64

The output from a D/A converter is true analog.

Question 65

Step size and proportionality factors are one and the same in the DAC input/output relationship.

Question 66

Resolution is inversely proportional to a number of bits.

Question 67

A digital- ramp ADC has the shortest conversion time of all ADC packages.

Question 68

D/A conversion accuracy is dependent on resistor precision and input voltage levels.

Question 69

R/2R ladder DACs use successive resistors, each having a value of 2 times the resistor preceding it.

Question 70

Offset error is really a component of any given particular circuit at zero volts and can normally be adjusted back to zero.

Question 71

Analog to digital conversion incorporates D/A conversion as a primary component.

Question 72

Many analog to digital conversions circuits require clock signals.

Question 73

A(n) is a device that converts a physical variable to an electrical variable.

Question 74

What type of ADCs are becoming popular since they require fewer port bits to input data and thereby reduce the cost of the interface with the rest of the data acquisition system?

Question 75

A(n) converts an analog input to a digital output.

Question 76

Increasing the number of subranging stages in a pipelined ADC increases the .

Question 77

A(n) converts a digital input to a proportional analog voltage or current.

Question 78

The analog signal from a DAC is often connected to some device or circuit that serves as a(n) to control the physical variable.

Question 79

Serial ADCs must have a built- in to convert the data to a bit stream.

Question 80

The of a DAC is the smallest change that can occur in the analog output as a result of a change in the digital input.