Deck 18: Multicore Computers

Question 1

The demand on power requirements has not grown as chip density and clock frequency have risen.

Answer 1

False

Question 2

An advantage of using a shared L2 cache on the chip is that data shared by multiple cores is not replicated at the shared cache level.

Answer 2

True

Question 3

_________ is when multiple pipelines are constructed by replicating execution resources,enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided.

A)Vectoring
B)Superscalar
C)Hybrid multithreading
D)Pipelining

Answer 3

B

Question 4

As chip transistor density has increased,the percentage of chip area devoted to memory has decreased.

Question 5

With _______,register banks are replicated so that multiple threads can share the use of pipeline resources.

A)SMT
B)pipelining
C)scalar
D)superscalar

Question 6

Database management systems and database applications are one area in which multicore systems can be used effectively.

Question 7

One way to control power density is to use more of the chip area for ________.

A)multicore
B)cache memory
C)silicon
D)resistors

Question 8

The potential performance benefits of a multicore organization depend on the ability to effectively exploit the parallel resources available to the application.

Question 9

The generic timer handles interrupt detection and interrupt prioritization.

Question 10

The big.Little architecture uses a combination of ARM Cortex-A7 and Cortex A-15 cores.

Question 11

The increasingly difficult engineering challenge related to processor logic is one of the reasons that an increasing fraction of the processor chip is devote to the simpler memory logic.

Question 12

With hybrid threading each major module is single threaded and the principal coordination involves synchronizing all the threads with a timeline thread.

Question 13

A potential advantage to having only dedicate L2 caches on the chip is that each core enjoys more rapid access to its private L2 cache.

Question 14

_________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline,another instruction is executing in another stage of the pipeline.

A)Superscalar
B)Scalar
C)Pipelining
D)Simultaneous multithreading

Question 15

With superscalar organization increased performance can be achieved by increasing the number of parallel pipelines.

Question 16

The ARM11 MPCore is an example of the L1 cache being divided into instruction and data caches.

Question 17

The organizational changes in processor design have primarily been focused on increasing instruction-level parallelism so that more work could be done in each clock cycle.

Question 18

Even if an individual application does not scale to take advantage of a large number of threads,it is still possible to gain from multicore architecture by running multiple instances of the application in parallel.

Question 19

___________ states that performance increase is roughly proportional to square root of increase in complexity.

A)Pollack's Rule
B)Moore's Law
C)Amdahl's Law
D)MOESI Rule

Question 20

Direct data intervention enables copying clean data from one CPU L1 data cache to another CPU L1 data cache without accessing external memory.

Question 21

__________ applications are characterized by having a small number of highly threaded processes.

Question 22

The GIC distributes interrupts to individual _________.

A)dies
B)cores
C)QPI
D)interconnects

Question 23

The Intel Core i7-990X chip supports _________ forms of external communications to other chips.

A)4
B)2
C)6
D)8

Question 24

Individual modules called systems are assigned to individual processors with ________ threading.

Question 25

_________ states that performance increase is roughly proportional to square root of increase in complexity.

Question 26

The _________ is an example of splitting off a separate,shared L3 cache,with dedicated L1 and L2 caches for each core processor.

A)IBM 370
B)ARM11 MPCore
C)AMD Opteron
D)Intel Core i7

Question 27

________ threading is when many similar or identical tasks are spread across multiple processors.

Question 28

_______ is an animation engine used by Valve for its games and licensed for other game developers.

Question 29

________ is a multithreaded process that provides scheduling and memory management for Java applications.

Question 30

The ________ is responsible for maintaining coherency among L1 data caches.

A)VFP unit
B)distributed interrupt controller
C)snoop control unit (SCU)
D)watchdog

Question 31

The principal building block of the IBM zEnterprise EC12 mainframe is the __________ .

Question 32

__________ applications are characterized by the presence of many single-threaded processes.

A)Java
B)Multithreaded native
C)Multi-instance
D)Multiprocess

Question 33

_________ applications are characterized by the presence of many single-threaded processes.

Question 34

________ threading involves the selective use of fine-grain threading for some systems and single threading for other systems.

Question 35

_______ law assumes a program in which a fraction (1- f )of the execution time involves code that is inherently serial and a fraction f that involves code that is infinitely parallelizable with no scheduling overhead.

Question 36

Putting rendering on one processor,AI on another,and physics on another is an example of _________ threading.

A)coarse-grained
B)multi-instance
C)fine-grained
D)hybrid

Question 37

__________ are characterized by the ability to support thousands of parallel execution threads

A)CPUs
B)QPIs
C)GPUs
D)ISAs

Question 38

_______ applications embrace threading in a fundamental way.

A)Multi-instance
B)Multi-process
C)Java
D)Threaded

Question 39

A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading.

A)multi-process
B)fine-grained
C)hybrid
D)coarse

Question 40

The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory.

A)migratory lines
B)DDI
C)VFP unit
D)IPIs

Question 41

The _________ is a cache-coherent,point-to-point link based electrical interconnect specification for Intel processors and chipsets that enable high-speed communications among connected processor chips.

Question 42

From the point of view of an A15 core,an interrupt can be active,inactive,or __________ .

Question 43

A single piece of silicon is called a ________.

Question 44

The most prominent trend in terms of heterogeneous multicore design is the use of both CPUs and __________ on the same chip.

Question 45

The SCU uses hybrid MESI and _________ protocols to maintain coherency between the individual L1 data caches and the L2 cache.