Essentials Of Computer Organization And Architecture 4th Edition by Linda Null,Julia Lobur

تمرين 41

With regard to Figure 7.11 and exercise 17, we have not provided for any type of error handling, such as if the address on the address lines were invalid, or the memory couldn't be read because of a hardware error. What could we do with our bus model to provide for such events
Reference of Exercise 17:
The protocol for a certain data bus is shown in the table below. Draw the corresponding timing diagram. You may refer to Figure 7.11.

Reference of Figure 7.11: