Deck 4: TTL Circuits, Karnaugh Maps, and Flip-Flops

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Question
Standard TTL circuits operate with a volt power supply.

A)2
B)4
C)5
D)3
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Question
A TTL gate may operate inadvertently as an                          

A)digital amplifier
B)analog amplifier
C)inverter
D)regulator
Question
Which statement below best describes a Karnaugh map?

A)it is simply a rearranged truth table
B)the karnaugh map eliminates the need for using nand and nor gates
C)variable complements can be eliminated by using karnaugh maps
D)a karnaugh map can be used to replace boolean rules
Question
Which of the examples below expresses the commutative law of multiplication?

A)a + b = b + a
B)a • b = b + a
C)a • (b • c) = (a • b) • c
D)a • b = b • a
Question
The Boolean expression Y = (AB)' is logically equivalent to what single gate?

A)nand
B)nor
C)and
D)or
Question
The systematic reduction of logic circuits is accomplished by:

A)symbolic reduction
B)ttl logic
C)using boolean algebra
D)using a truth table
Question
Each "1" entry in a K-map square represents:

A)a high for each input truth table condition that produces a high output
B)a high output on the truth table for all low input combinations
C)a low output for all possible high input conditions
D)a don't care condition for all possible input truth table combinations
Question
Each "0" entry in a K-map square represents:

A)a high for each input truth table condition that produces a high output
B)a high output on the truth table for all low input combinations
C)a low output for all possible high input conditions
D)a don't care condition for all possible input truth table combinations
Question
Looping on a K-map always results in the elimination of                      

A)variables within the loop that appear only in their complemented form
B)variables that remain unchanged within the loop
C)variables within the loop that appear in both complemented and uncomplemented form
D)variables within the loop that appear only in their uncomplemented form
Question
Which of the following expressions is in the sum-of-products form?

A)(a + b)(c + d)
B)(a * b)(c * d)
C)a* b *(cd)
D)a * b + c * d
Question
What is an ambiguous condition in a NAND based S'-R' latch?

A)s'=0, r'=1
B)s'=1, r'=0
C)s'=1, r'=1
D)s'=0, r'=0
Question
In a NAND based S'-R' latch, if S'=1 & R'=1 then the state of the latch is

A)no change
B)set
C)reset
D)forbidden
Question
A NAND based S'-R' latch can be converted into S-R latch by placing                          

A)a d latch at each of its input
B)an inverter at each of its input
C)it can never be converted
D)both a d latch and an inverter at its input
Question
The difference between a flip-flop & latch is                          

A)both are same
B)flip-flop consist of an extra output
C)latches has one input but flip-flop has two
D)latch has two inputs but flip-flop has one
Question
How many types of flip-flops are?

A)2
B)3
C)4
D)5
Question
The S-R flip flop consist of                          

A)4 and gates
B)two additional and gates
C)an additional clock input
D)3 and gates
Question
What is one disadvantage of an S-R flip-flop?

A)it has no enable input
B)it has a race condition
C)it has no clock input
D)invalid state
Question
One example of the use of an S-R flip-flop is as                          

A)racer
B)stable oscillator
C)binary storage register
D)transition pulse generator
Question
When is a flip-flop said to be transparent?

A)when the q output is opposite the input
B)when the q output follows the input
C)when you can see through the ic packaging
D)when the q output is complementary of the input
Question
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when

A)the clock pulse is low
B)the clock pulse is high
C)the clock pulse transitions from low to high
D)the clock pulse transitions from high to low
Question
What is the hold condition of a flip-flop?

A)both s and r inputs activated
B)no active s or r input
C)only s is active
D)only r is active
Question
One example of the use of an S-R flip-flop is as                        

A)transition pulse generator
B)racer
C)switch debouncer
D)astable oscillator
Question
The truth table for an S-R flip-flop has how many VALID entries?

A)1
B)2
C)3
D)4
Question
When both inputs of a J-K flip-flop cycle, the output will                        

A)be invalid
B)change
C)not change
D)toggle
Question
Which of the following is correct for a gated D-type flip-flop?

A)the q output is either set or reset as soon as the d input goes high or low
B)the output complement follows the input when enabled
C)only one of the inputs can be high at a time
D)the output toggles if one of the inputs is held high
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Deck 4: TTL Circuits, Karnaugh Maps, and Flip-Flops
1
Standard TTL circuits operate with a volt power supply.

A)2
B)4
C)5
D)3
5
2
A TTL gate may operate inadvertently as an                          

A)digital amplifier
B)analog amplifier
C)inverter
D)regulator
analog amplifier
3
Which statement below best describes a Karnaugh map?

A)it is simply a rearranged truth table
B)the karnaugh map eliminates the need for using nand and nor gates
C)variable complements can be eliminated by using karnaugh maps
D)a karnaugh map can be used to replace boolean rules
it is simply a rearranged truth table
4
Which of the examples below expresses the commutative law of multiplication?

A)a + b = b + a
B)a • b = b + a
C)a • (b • c) = (a • b) • c
D)a • b = b • a
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5
The Boolean expression Y = (AB)' is logically equivalent to what single gate?

A)nand
B)nor
C)and
D)or
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6
The systematic reduction of logic circuits is accomplished by:

A)symbolic reduction
B)ttl logic
C)using boolean algebra
D)using a truth table
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k this deck
7
Each "1" entry in a K-map square represents:

A)a high for each input truth table condition that produces a high output
B)a high output on the truth table for all low input combinations
C)a low output for all possible high input conditions
D)a don't care condition for all possible input truth table combinations
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8
Each "0" entry in a K-map square represents:

A)a high for each input truth table condition that produces a high output
B)a high output on the truth table for all low input combinations
C)a low output for all possible high input conditions
D)a don't care condition for all possible input truth table combinations
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k this deck
9
Looping on a K-map always results in the elimination of                      

A)variables within the loop that appear only in their complemented form
B)variables that remain unchanged within the loop
C)variables within the loop that appear in both complemented and uncomplemented form
D)variables within the loop that appear only in their uncomplemented form
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k this deck
10
Which of the following expressions is in the sum-of-products form?

A)(a + b)(c + d)
B)(a * b)(c * d)
C)a* b *(cd)
D)a * b + c * d
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k this deck
11
What is an ambiguous condition in a NAND based S'-R' latch?

A)s'=0, r'=1
B)s'=1, r'=0
C)s'=1, r'=1
D)s'=0, r'=0
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12
In a NAND based S'-R' latch, if S'=1 & R'=1 then the state of the latch is

A)no change
B)set
C)reset
D)forbidden
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13
A NAND based S'-R' latch can be converted into S-R latch by placing                          

A)a d latch at each of its input
B)an inverter at each of its input
C)it can never be converted
D)both a d latch and an inverter at its input
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14
The difference between a flip-flop & latch is                          

A)both are same
B)flip-flop consist of an extra output
C)latches has one input but flip-flop has two
D)latch has two inputs but flip-flop has one
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15
How many types of flip-flops are?

A)2
B)3
C)4
D)5
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16
The S-R flip flop consist of                          

A)4 and gates
B)two additional and gates
C)an additional clock input
D)3 and gates
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17
What is one disadvantage of an S-R flip-flop?

A)it has no enable input
B)it has a race condition
C)it has no clock input
D)invalid state
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18
One example of the use of an S-R flip-flop is as                          

A)racer
B)stable oscillator
C)binary storage register
D)transition pulse generator
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k this deck
19
When is a flip-flop said to be transparent?

A)when the q output is opposite the input
B)when the q output follows the input
C)when you can see through the ic packaging
D)when the q output is complementary of the input
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Unlock for access to all 25 flashcards in this deck.
Unlock Deck
k this deck
20
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when

A)the clock pulse is low
B)the clock pulse is high
C)the clock pulse transitions from low to high
D)the clock pulse transitions from high to low
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21
What is the hold condition of a flip-flop?

A)both s and r inputs activated
B)no active s or r input
C)only s is active
D)only r is active
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22
One example of the use of an S-R flip-flop is as                        

A)transition pulse generator
B)racer
C)switch debouncer
D)astable oscillator
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23
The truth table for an S-R flip-flop has how many VALID entries?

A)1
B)2
C)3
D)4
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24
When both inputs of a J-K flip-flop cycle, the output will                        

A)be invalid
B)change
C)not change
D)toggle
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25
Which of the following is correct for a gated D-type flip-flop?

A)the q output is either set or reset as soon as the d input goes high or low
B)the output complement follows the input when enabled
C)only one of the inputs can be high at a time
D)the output toggles if one of the inputs is held high
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