Deck 6: Flip-Flops and Mosfets in IC Components

Question 1

A technique used to reduce the magnitude of threshold voltage of MOSFET is the

A)use of complementary mosfet
B)use of silicon nitride
C)using thin film technology
D)increasing potential of the channel

Answer 1

use of silicon nitride

Question 2

What is used to higher the speed of operation in MOSFET fabrication?

A)ceramic gate
B)silicon dioxide
C)silicon nitride
D)poly silicon gate

Answer 2

poly silicon gate

Question 3

Why MOSFET is preferred over BJT in IC components?

A)mosfet has low packing density
B)mosfet has medium packing density
C)mosfet has high packing density
D)mosfet has no packing density

Answer 3

mosfet has low packing density

Question 4

Critical defects per unit chip area is for a MOS transistor.

A)high
B)low
C)neutral
D)very high

Question 5

MOS is being used in                        

A)lsi
B)vlsi
C)msi
D)both lsi and vlsi

Question 6

The D flip-flop has input.

A)1
B)2
C)3
D)4

Question 7

The D flip-flop has output/outputs.

A)2
B)3
C)4
D)1

Question 8

A D flip-flop can be constructed from an _ flip-flop.

A)s-r
B)j-k
C)t
D)s-k

Question 9

In D flip-flop, if clock input is HIGH & D=1, then output is                        

A)0
B)1
C)forbidden
D)toggle

Question 10

Which of the following is correct for a gated D flip-flop?

A)the output toggles if one of the inputs is held high
B)only one of the inputs can be high at a time
C)the output complement follows the input when enabled
D)q output follows the input d when the enable is high

Question 11

With regard to a D latch                  

A)the q output follows the d input when en is low
B)the q output is opposite the d input when en is low
C)the q output follows the d input when en is high
D)the q output is high regardless of en's input state

Question 12

Which of the following is correct for a D latch?

A)the output toggles if one of the inputs is held high
B)q output follows the input d when the enable is high
C)only one of the inputs can be high at a time
D)the output complement follows the input when enabled

Question 13

Which of the following describes the operation of a positive edge-triggered D flip-flop?

A)if both inputs are high, the output will toggle
B)the output will follow the input on the leading edge of the clock
C)when both inputs are low, an invalid state exists
D)the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock

Question 14

A positive edge-triggered D flip-flop will store a 1 when                  

A)the d input is high and the clock transitions from high to low
B)the d input is high and the clock transitions from low to high
C)the d input is high and the clock is low
D)the d input is high and the clock is high

Question 15

Why do the D flip-flops receive its designation or nomenclature as 'Data Flip-flops'?

A)due to its capability to receive data from flip-flop
B)due to its capability to store data in flip-flop
C)due to its capability to transfer the data into flip-flop
D)due to erasing the data from the flip-flop

Question 16

The characteristic equation of D-flip-flop implies that                        

A)the next state is dependent on previous state
B)the next state is dependent on present state
C)the next state is independent of previous state
D)the next state is independent of present state

Question 17

The asynchronous input can be used to set the flip-flop to the                          

A)1 state
B)0 state
C)either 1 or 0 state
D)forbidden state

Question 18

Input clock of RS flip-flop is given to                          

A)input
B)pulser
C)output
D)master slave flip-flop

Question 19

D flip-flop is a circuit having                          

A)2 nand gates
B)3 nand gates
C)4 nand gates
D)5 nand gates

Question 20

At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

A)conversion condition
B)race around condition
C)lock out state
D)forbidden state

Question 21

Master slave flip flop is also referred to as?

A)level triggered flip flop
B)pulse triggered flip flop
C)edge triggered flip flop
D)edge-level triggered flip flop

Question 22

In a positive edge triggered JK flip flop, a low J and low K produces?

A)high state
B)low state
C)toggle state
D)no change state

Question 23

If one wants to design a binary counter, the preferred type of flip-flop is                          

A)d type
B)s-r type
C)latch
D)j-k type

Question 24

S-R type flip-flop can be converted into D type flip-flop if S is connected to R through

A)or gate
B)and gate
C)inverter
D)full adder

Question 25

Which of the following flip-flops is free from the race around the problem?

A)t flip-flop
B)sr flip-flop
C)master-slave flip-flop
D)d flip-flop