Deck 7: Latches, Flip-Flops, and Timers

Question 1

All multivibrators require feedback.

Answer 1

True

Question 2

All multivibrators are level triggered.

Answer 2

False

Question 3

The symbol for an edge- triggered flip- flop has a triangle on its clock input.

Answer 3

True

Question 4

A D flip- flop is constructed by connecting an inverter between the Set and Clock terminals of a S- R flip- flop.

Question 5

The J- K flip- flop toggles when both inputs are high during the transition of the clock signal.

Question 6

Preset and Clear inputs are normally synchronous.

Question 7

A pulse- triggered flip- flop is identified by a bubble on its Q output terminal.

Question 8

A one- shot is a multivibrator that must be triggered to produce each output pulse.

Question 9

The 555 timer has three basic operating modes: monostable, bistable, and astable.

Question 10

The waveforms for this J- K flip- flop indicate the circuit is operating properly.

Question 11

The ON time of a 555 monostable multivibrator is determined by t_w = 1.1RC.

Question 12

A diode can be added to the discharge path for a 555 astable multivibrator to obtain duty cycles that are less than 50%.

Question 13

An active- HIGH input S- R latch has a 1 on the S input and a 0 on the R input. What state is the latch in?

A) Q = 0, = 1
B) Q = 1, = 0
C) Q = 1, = 1
D) Q = 0, = 0

Question 14

What advantage does a J- K flip- flop have over an R- S flip- flop?

A) It does not require a clock input.
B) It has only one output.
C) It has no invalid input states.
D) It has fewer gates.

Question 15

A J- K flip- flop can be used as a divide- by- two frequency divider with an output duty cycle of 50%.

Question 16

How is the invalid input state problem associated with the S- R flip- flop overcome?

A) The R terminal is eliminated.
B) A single input terminal is used (D).
C) The R input is fed through an inverter.
D) Both B and C are correct.

Question 17

Which of the following is correct for a gated D latch?

A) The output toggles if one of the inputs is held high.
B) Only one of the inputs can be high at a time.
C) Q output follows the input D when the ENABLE is high.
D) The output complement follows the input when enabled.

Question 18

What symbol is used to identify edge- triggered flip- flops?

A) An inverted "L" on the output
B) The letter E on the Enable input
C) A triangle on the Clock input
D) A bubble on the Clock input

Question 19

An edge- triggered flip- flop must have ______.

A) at least two inputs to handle rising and falling edges
B) a pulse transition detector
C) a very fast response time
D) active- low inputs and complemented outputs

Question 20

What primary advantage does the J- K flip- flop have over the S- R flip- flop?

A) The J- K flip- flop does not have propagation delay problems.
B) The J- K flip- flop does not have an invalid input state.
C) The J- K flip- flop is much faster.
D) The J- K flip- flop only needs one output.

Question 21

If both inputs of an S- R flip- flop are low, what happens when the clock goes high?

A) The output toggles.
B) An invalid state is produced.
C) The output resets.
D) No change occurs in the output.

Question 22

Asynchronous inputs are best described as________.

A) having little or no control over the FF, except during the active clock input
B) being tied to the clock, but not to the inputs
C) being tied to the inputs, but independent of the clock
D) having full control over the FF, regardless of the input or clock states

Question 23

The asynchronous inputs to a flip- flop are normally labeled_____and________ , and are normally active_______inputs.

A) START, STOP, low
B) SET, RESET, high
C) PRE, CLR, low
D) ON, OFF, high

Question 24

Pulse- triggered flip- flops are also called_______flip- flops.

A) postponed
B) master- slave
C) edge
D) level

Question 25

Which of the following best describes the action of pulse- triggered flip- flops?

A) A pulse on the clock transfers data from input to output.
B) The synchronous inputs must be pulsed.
C) The clock and R- S inputs must be pulse shaped.
D) The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.

Question 26

When both inputs of a J- K pulse- triggered FF are high, and the clock cycles, the output wil_________

A) remain unchanged
B) be invalid
C) toggle
D) not change

Question 27

The L in 74L71 stands for _______.

A) low power
B) the type of package
C) lock- out flip- flop
D) low frequency

Question 28

Which of the following is a primary characteristic of the data lock- out flip- flop?

A) Data can only be entered when the clock is high.
B) Data is only clocked into the FF on the clock transition.
C) Data cannot be entered into the FF unless the EN line is high.
D) The master section is a pulse triggered type FF.

Question 29

Which of the following ratings is not associated with flip- flops?

A) Set- up time
B) Propagation delay time
C) Hold time
D) Interval time

Question 30

Set- up time specifies ________ .

A) how long it takes the output to change states after the clock has transitioned
B) the maximum time interval required for the control levels to remain on the inputs before the triggering edge of the clock in order for the data to be reliably clocked out of the FF
C) the minimum time required for the control levels to be maintained at the inputs of a flip- flop prior to the triggering edge of the clock in order for data to be reliably clocked into the component
D) how long the operator has in order to get the flip- flop running before the maximum power level is exceeded

Question 31

These waveforms are applied to a gated D latch, which is initially RESET. Which of the areas identified on the Q waveform is incorrect?

A) Area a
B) Area b
C) Area c
D) Area d

Question 32

Flip- flops are normally used for all of the following applications, except _________.

A) logic gates
B) frequency division
C) data storage
D) counting

Question 33

A J- K flip- flop is being used as a divide- by- 2 circuit when _________.

A) the J and K inputs are tied to Vcc
B) the reset is tied to the clock
C) the J and K inputs are tied to ground
D) all the inputs are connected to the preset

Question 34

A one- shot is classified as a(n) _________.

A) one- pulse multivibrator
B) bistable multivibrator
C) astable multivibrator
D) monostable multivibrator

Question 35

A retriggerable one- shot has a pulse width of 10 ms. Three milliseconds (3 ms) after being triggered, another trigger pulse is applied. The duration of the resulting output pulse will be_________ms

A) 10
B) 3
C) 7
D) 13

Question 36

An astable multivibrator is a circuit that _________.

A) has two stable states
B) has one stable state
C) produces a continuous output signal
D) Both B and C are correct.

Question 37

A push- button switch is used to input data to a register. The output of the register is erratic. Which of the following could be the cause of the problem?

A) The power supply is probably noisy.
B) The socket contacts on the register IC are corroded.
C) The switch contacts are bouncing.
D) The register IC is intermittent and failure is imminent.

Question 38

A positive edge- triggered J- K flip- flop is used to produce a two- phase clock. However, when the circuit is operated it produces erratic results. Close examination with an oscilloscope reveals the presence of glitches. What might be the source of these glitches?

A) A race condition exists between the J and K inputs.
B) The PRESET and CLEAR terminals may have been left floating.
C) A race condition exists between the Q and Q outputs to the AND gate.
D) A race condition exists between the CLOCK and the outputs of the flip- flop feeding the AND gate.