Deck 3: Logic Gates

Question 1

A LOW input to an inverter produces a HIGH output.

Answer 1

True

Question 2

The OR gate performs a function similar to series- connected switches.

Answer 2

False

Question 3

The output of an AND gate is HIGH only when all inputs are HIGH.

Answer 3

True

Question 4

The output of an AND gate is LOW only when all inputs are LOW.

Question 5

When the inputs to a 3- input AND gate are 001, the output is HIGH.

Question 6

When the inputs to a 3- input OR gate are 001, the output is HIGH.

Question 7

The output of an OR gate is HIGH when at least one input is HIGH.

Question 8

The output of an OR gate is LOW when at least one input is LOW.

Question 9

The output of a NAND gate is HIGH only when one or more inputs are HIGH.

Question 10

The output of a NAND gate is LOW only when all inputs are HIGH.

Question 11

The output of a NOR gate is LOW only when all inputs are HIGH.

Question 12

The output of a NOR gate is HIGH only when all inputs are HIGH.

Question 13

When the inputs to a 3- input NAND gate are 001, the output is HIGH.

Question 14

When the inputs to a 3- input NOR gate are 001, the output is LOW.

Question 15

The output of a 2- input Exclusive- OR gate is HIGH when the inputs are equal, or identical.

Question 16

The output of a 2- input Exclusive- NOR gate is HIGH when the inputs are equal, or identical.

Question 17

A circle, or "bubble," on a distinctive- shape logic symbol indicates a logic inversion.

Question 18

The symbol below represents a(n)_________ .

A) NAND gate
B) OR gate
C) AND gate
D) none of the above

Question 19

The symbol below represents a(n) ________.
?

A) OR gate
B) NAND gate
C) AND gate
D) none of the above

Question 20

The symbol below represents a(n) _________.

A) OR gate
B) AND gate
C) Inverter
D) none of the above

Question 21

The symbol below represents a(n) _________ .

A) OR gate
B) AND gate
C) Inverter
D) none of the above

Question 22

The symbol below represents a(n) _________.

A) NAND gate
B) AND gate
C) OR gate
D) Inverter

Question 23

The symbol below represents a(n) _________.

A) inverter
B) NOR gate
C) Exclusive- NOR gate
D) NAND gate

Question 24

The symbol below represents a(n) _________.

A) Exclusive- NOR gate
B) NAND gate
C) NOR gate
D) inverter

Question 25

The symbol below represents a(n)_________

A) NOR gate
B) AND gate
C) NAND gate
D) OR gate

Question 26

The symbol below represents a(n) _________.

A) NAND gate
B) AND gate
C) Exclusive- OR gate
D) OR gate

Question 27

The symbol below represents a(n) _________ .

A) Exclusive- NOR gate
B) Exclusive- OR gate
C) NAND gate
D) NOR gate

Question 28

The symbol below represents a(n) _________.

A) NAND gate
B) AND gate
C) Inverter
D) OR gate

Question 29

The truth table below describes a(n) _________ .

A) AND gate
B) OR gate
C) NOR gate
D) NAND gate

Question 30

The truth table below describes a(n) _________ .

A) AND gate
B) OR gate
C) NOR gate
D) NAND gate

Question 31

The truth table below describes a(n) ________
?

A) AND gate
B) OR gate
C) NOR gate
D) NAND gate

Question 32

The truth table below describes a(n) _________ .

A) AND gate
B) OR gate
C) NOR gate
D) NAND gate

Question 33

Which of the truth tables below describes the Exclusive- NOR gate?

A) (A)
B) (B)
C) (C)
D) (D)

Question 34

The timing diagram below is correct for a 2- input _________ gate.

A) AND
B) OR
C) NAND
D) Exclusive- OR

Question 35

The timing diagram below is correct for a 2- input _________ gate.

A) AND
B) OR
C) NAND
D) Exclusive-OR

Question 36

The timing diagram below is correct for a 2-input ________ gate
?

A) AND
B) OR
C) NAND
D) Exclusive- OR

Question 37

The timing diagram below is correct for a 2- input _________gate.

A) Exclusive- NOR
B) OR
C) AND
D) NOR

Question 38

The timing diagram below is correct for a 2- input _________ gate.

A) AND
B) NAND
C) Exclusive- NOR
D) Exclusive- OR

Question 39

The timing diagram below is correct for a 2- input _________ gate.

A) Exclusive- OR
B) AND
C) Exclusive- NOR
D) NAND

Question 40

IC's with a _________prefix have a broad operating temperature range and are generally used by the military.

A) 74
B) 54
C) TTL
D) 2N

Question 41

The _________series of IC's are pin, function and voltage- level compatible with the 74 series IC's.

A) 2N
B) ALS
C) CMOS
D) HCT

Question 42

A logic gate draws 10mA when its output is HIGH and 20mA when its output is LOW. When operating from a 12V supply with a 10% duty cycle the average power dissipation will be_________.

A) 180mW
B) 228mW
C) 324mW
D) 360mW

Question 43

The fanout for standard bipolar logic devices is _________ .

A) 10
B) 5
C) 1
D) 2

Question 44

The term "hex inverter" refers to _________.

A) six inverters in a single package
B) an inverter that has a history of failure
C) an inverter which has six inputs
D) a six- input symbolic logic device

Question 45

Which type of gate can be used to add two bits?

A) XOR
B) XNAND
C) NOR
D) NAND

Question 46

An AND gate is checked for operation and the following readings are taken on the gate: input A = 0.2 V, input B = 4.5 V, input C = 0.4 V, output = 4.9 V. What might be wrong with the gate?

A) Input C is too high.
B) Nothing is wrong with the gate.
C) The output is too low: it should be 5 V.
D) The output is stuck high; the chip is bad.

Question 47

When an open occurs on the input to a bipolar logic device, the output will _________ .

A) go LOW, because there is no current in an open circuit
B) go HIGH, since full voltage appears across an open
C) react to the open input as if it were a HIGH input
D) still be good, if only the good inputs are used

Question 48

When an open occurs on the input of a CMOS gate, the output will _________ .

A) be treated as if the open input were a HIGH
B) go LOW, because there is no current in an open circuit
C) go HIGH, since full voltage appears across an open
D) be unpredictable; it may go HIGH or LOW

Question 49

What technology allows a GAL to be reprogrammed again and again?

A) E²CMOS
B) NMOS
C) CMOS
D) TTL

Question 50

What programmable arrays are in PLD's?

A) NOR arrays
B) AND arrays only
C) OR arrays only
D) OR arrays and AND arrays

Question 51

Which of the following is not a type of SPLD?

A) RAM
B) PROM
C) PLA
D) GAL

Question 52

HDL stands for _________ .

A) hardwired digital logic
B) hardware description language
C) hardwire descriptive logic
D) none of the above

Question 53

HDLs differ from_________ in that they include ways of describing propagation times and other logic characteristics.

A) software digital logic
B) software programming languages
C) software description languages
D) none of the above

Question 54

The_________in a VHDL program defines the logic element and its inputs/outputs or ports.

A) source
B) architecture
C) entity
D) hardware

Question 55

The_________in a VHDL program describes its logic operation.

A) entity
B) hardware
C) architecture
D) source

Question 56

A __________ IC comes with logic functions that are not programmed in and cannot be altered.

A) fixed- function
B) VHDL
C) HDL
D) microcontroller