Deck 3: Operating System Hardware Components

Question 1

You have found an old dusty computer in your basement that you can identify as an original IBM PC. You ask your friend if he knows what CPU was used in these computers. Which of the following represents a correct response to your question?

A) 8088
B) Pentium
C) 80286
D) Itanium

Answer 1

A

Question 2

You have heard that the Linux distribution your are going to install to run a new application runs best on a RISC architecture. Which of the following CPU families should you consider for the computer on which you will install this Linux distribution?

A) Motorola 68040
B) Intel Xeon
C) SPARC
D) Pentium

Answer 2

C

Question 3

Approximately how much data could a CPU with an external clock speed of 2 GHz and a 32-bit data bus transfer per second?

A) 4 Gigabits
B) 8 Gigabits
C) 4 Gigabytes
D) 8 Gigabytes

Answer 3

D

Question 4

Which of the following is best described as a technology that enables a single processor to appear as two processors to the OS and allows multiple threads to run simultaneously?

A) EPIC
B) hyper-threading
C) RISC
D) super-threading

Question 5

Which feature of RISC CPUs allows the processor to operate on one instruction at the same time it is fetching one or more subsequent instructions?

A) caching
B) CPU scheduling
C) coprocessing
D) pipelining

Question 6

You are building a new PC for yourself. You want your computer to have a dual-core processor made by AMD. Which processor family should you choose?

A) K6-2
B) Duron
C) Athlon X2
D) Athlon XP

Question 7

You work for a college that was just donated a computer with an Itanium processor. Which of the following OSs can NOT be installed on this computer?

A) Windows XP 64-bit
B) Vista 64-bit
C) Windows Server 2003 Enterprise Edition 64-bit
D) Windows Server 2008 64-bit

Question 8

Clock speed and CPU design are factors that determine how fast instructions are executed.

Question 9

A CPU that has two or more sections that read and execute instructions is referred to as which of the following?

A) multiprocessor CPU
B) single-CPU system
C) multicore processor
D) multibus processor

Question 10

Which of the following is true about RISC CPU hardware?

A) it is less complicated and can run at faster clock speeds
B) it is more complicated and must run at slower clock speeds
C) it cannot run in small devices like smartphones
D) all current CPUs are based on it

Question 11

The address bus almost always runs faster than the external clock speed of the CPU.

Question 12

The Intel Itanium processor is a CISC-based processor that uses a 32-bit architecture.

Question 13

You are troubleshooting a computer that is in the design phase. The problem you see is that the CPU is not receiving information about the status and of resources and devices connected to the computer. The CPU is also not receiving IRQs.What component of the computer do you suspect could be the problem?

A) CPU cache
B) data bus
C) control bus
D) address bus

Question 14

If you are designing a CPU on which you want to have a lot of storage that can be accessed at the internal clock speed of the CPU,which type of memory are you concerned with?

A) L2 RAM
B) L2 cache
C) L1 cache
D) L1 RAM

Question 15

A RISC CPU performs more complex instructions and can work on general-purpose hardware.

Question 16

If you want to design a CPU that will run on general-purpose hardware,which type of CPU should you design?

A) CISC
B) single-threaded
C) multicore
D) RISC

Question 17

If your address bus is 20-bits wide,approximately how much memory can your computer address?

A) 64K bytes
B) 1024K bytes
C) 4G bits
D) 64K bits

Question 18

Which hardware component predicts what data will be needed and makes that data available to the CPU's internal memory?

A) cache controller
B) data bus
C) address bus
D) RAM controller

Question 19

CPUs that run faster generally require more energy and generate more heat.

Question 20

What RISC processor design can build multiple instructions into a single word and can combine instructions into groups,allowing parallel operation?

A) pipelining
B) EPIC
C) instruction caching
D) complex instruction set

Question 21

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
the speed at which the processor communicates with the memory and other devices in the computer

Question 22

_________________ allows the processor to operate on one instruction at the same time that is fetches subsequent instructions.

Question 23

What is the difference between L1 cache and L2 cache?

Question 24

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
first-level cache in a XEON CPU that stores decoded instructions
and delivers them to the processor at high speed.

Question 25

Describe the difference between the internal and external clock speeds of a CPU.

Question 26

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
the part of a processor used to read and execute instructions

Question 27

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
the group of commands the processor recognizes

Question 28

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
an internal communications pathway that allows computer components,such as the CPU,display adapter,and main memory,to share information

Question 29

The ability of a single EPIC processor to perform the instructions in an instruction group simultaneously is ______________ operation.

Question 30

Describe the difference between a multiprocessor computer and a multicore computer.

Question 31

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
internal communications pathway that keeps the CPU informed of the
status of particular computer resources and devices

Question 32

The ___________________ is the list of command the CPU can execute.

Question 33

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
an Intel multithreading technology that enables a single processor
to appear to the operating system as two separate processors

Question 34

A CPU scheduling algorithm that allows two or more processes to be run at the same time by a single CPU is called __________________.

Question 35

Describe what is meant by a computer's system architecture.

Question 36

A computer with two or more CPUs is referred to as a ________________ computer.

Question 37

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
computer CPU architecture in which processor components are reconfigured to conduct different operations as required

Question 38

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
a computer CPU design that dedicates processor hardware components to certain functions

Question 39

MATCHING
a.CISC
b.external clock speed
c.data bus
d.address bus
e.core
f.hyper-threading
g.control bus
h.instruction set
i.RISC
j.execution-based cache
an internal communications pathway for memory reads and writes

Question 40

Describe the difference between a RISC and CISC CPU.

Question 41

List the three types of bus that you will find in every computer design.