Deck 3: A Top-Level View of Computer Function and Interconnection

Question 1

A(n)_________ is generated by a failure such as power failure or memory parity error.

A)I / O interrupt
B)hardware failure interrupt
C)timer interrupt
D)program interrupt

Answer 1

B

Question 2

The von Neumann architecture is based on which concept?

A)data and instructions are stored in a single read-write memory
B)the contents of this memory are addressable by location
C)execution occurs in a sequential fashion
D)all of the above

Answer 2

D

Question 3

A sequence of codes or instructions is called __________.

A)software
B)memory
C)an interconnect
D)a register

Answer 3

A

Question 4

A key characteristic of a bus is that it is not a shared transmission medium.

Question 5

Program execution consists of repeating the process of instruction fetch and instruction execution.

Question 6

The method of using the same lines for multiple purposes is known as time multiplexing.

Question 7

Computer systems contain a number of different buses that provide pathways between components at various levels of the computer system hierarchy.

Question 8

Interrupts do not improve processing efficiency.

Question 9

Timing refers to the way in which events are coordinated on the bus.

Question 10

Because all devices on a synchronous bus are tied to a fixed clock rate,the system cannot take advantage of advances in device performance.

Question 11

It is not possible to connect I / O controllers directly onto the system bus.

Question 12

The basic function of a computer is to execute programs.

Question 13

An I / O module cannot exchange data directly with the processor.

Question 14

The unit of transfer at the link layer is a phit and the unit transfer at the physical layer is a flit.

Question 15

In general,the more devices attached to the bus,the greater the bus length and hence the greater the propagation delay.

Question 16

With asynchronous timing the occurrence of events on the bus is determined by a clock.

Question 17

At a top level,a computer consists of CPU,memory,and I / O components.

Question 18

The processing required for a single instruction is called a(n)__________ cycle.

A)execute
B)fetch
C)instruction
D)packet

Question 19

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies,Princeton.

A)John Maulchy
B)John von Neumann
C)Herman Hollerith
D)John Eckert

Question 20

A key requirement for PCIe is high capacity to support the needs of higher data rate I / O devices such as Gigabit Ethernet.

Question 21

The data lines provide a path for moving data among system modules and are collectively called the _________.

A)control bus
B)address bus
C)data bus
D)system bus

Question 22

A _________ register contains the data to be written into memory or receives the data read from memory.

Question 23

The collection of paths connecting the various modules is called the _________ structure.

Question 24

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

A)transaction layer
B)root layer
C)configuration layer
D)transport layer

Question 25

A(n)_________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

Question 26

A __________ is a communication pathway connecting two or more devices.

Question 27

Each data path consists of a pair of wires (referred to as a __________ )that transmits data one bit at a time.

A)lane
B)path
C)line
D)bus

Question 28

There are three important groups of DLLPs used in managing a link: flow control packets,??????????_________________ ,and TLP ACK and NAK packets.

Question 29

The _________ lines are used to control the access to and the use of the data and address lines.

Question 30

A __________ register specifies the address in memory for the next read or write.

Question 31

A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.

Question 32

The TL supports which of the following address spaces?

A)memory
B)I / O
C)message
D)all of the above

Question 33

The __________ are used to designate the source or destination of the data on the data bus.

A)system lines
B)data lines
C)control lines
D)address lines

Question 34

A __________ is the high-level set of rules for exchanging packets of data between devices.

A)bus
B)protocol
C)packet
D)QPI

Question 35

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

A)link
B)protocol
C)routing
D)physical

Question 36

The most common classes of interrupts are: program,timer,I / O and ________.

Question 37

A(n)_________ is generated by some condition that occurs as a result of an instruction execution.

A)timer interrupt
B)I / O interrupt
C)program interrupt
D)hardware failure interrupt

Question 38

A bus that connects major computer components (processor,memory,I / O)is called a __________.

A)system bus
B)address bus
C)data bus
D)control bus

Question 39

A(n)________ interrupt is generated by an I / O controller to signal normal completion of an operation,request service from the processor,or to signal a variety of error conditions.

Question 40

The interconnection structure must support which transfer?

A)memory to processor
B)processor to memory
C)I / O to or from memory
D)all of the above

Question 41

With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.

Question 42

The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.

Question 43

The __________ is a popular high-bandwidth,processor-independent bus that can function as a mezzanine or peripheral bus.

Question 44

The purpose of the PCIe __________ layer is to ensure reliable delivery of packets across the PCIe link.

Question 45

The QPI link layer performs two key functions: flow control and _________ control.