Deck 19: General-Purpose Graphic Processing Units
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Deck 19: General-Purpose Graphic Processing Units
1
All but one set of GPU processor cores will be idle,while one SM is bearing the full processing load.
True
2
The total number of threads defined is typically in the thousands to maximize the utilization of the GPU processor cores as well as maximize the available speedup.
True
3
Because the GPU and the CPU are designed and optimized for two significantly different types of applications,their architectures differ significantly.
True
4
GPGPU is a computing platform and programming model created by NVIDIA.
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5
The GPU is most efficient when it is processing as many warps as possible to keep the CUDA cores maximally utilized.
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6
For about $200 you can purchase a GPU with 960 parallel processor cores for a workstation.
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7
The Fermi architecture upgraded from the IEEE 754-1985 floating-point arithmetic standard to the IEEE 754-2008 standard.
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8
In embedded systems the GPU is composed of only a single-digit number of cores,and are typically combined with a number of conventional cores,referred to as _________.
A)arithmetic logic units
B)control units
C)central processing units
D)graphic processing units
A)arithmetic logic units
B)control units
C)central processing units
D)graphic processing units
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9
It is not important for the programmer to understand the nuances of the various GPU memories.
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10
The largest GPUs are found in embedded systems.
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11
The equivalent GPU hardware component for a block is the CUDA multiprocessor (SM).
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12
CUDA was created by __________ .
A)Amdahl
B)NVIDIA
C)the U.S.Government
D)Herbert Moore
A)Amdahl
B)NVIDIA
C)the U.S.Government
D)Herbert Moore
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13
GPUs can be found in almost all of today's workstations,laptops, tablets,and smartphones.
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14
A kernel typically will have few to no branching statements.
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15
A SoC product architect can create product families or a specific product within a family by placing a single slice or multiple slices on a SoC chip.
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16
The __________ is designed specifically to be optimized for fast three-dimensional (3D)graphics rendering and video processing.
A)CPU
B)GPU
C)CU
D)ALU
A)CPU
B)GPU
C)CU
D)ALU
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17
A group of threads assigned to a particular SM is a __________ .
A)block
B)grid
C)unit
D)kernel
A)block
B)grid
C)unit
D)kernel
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18
An instance of the kernel on the GPU is a ___________ .
A)thread
B)warp
C)grid
D)block
A)thread
B)warp
C)grid
D)block
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19
The grid and the block need to have the same dimensions.
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20
CUDA C is a C / C++ based language.
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21
The data-parallel code to be run on the GPU is called a ___________ .
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22
The entire Gen8 compute architecture interfaces to the rest of the SoC components via a dedicated unit called the ____________ .
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23
A __________ program can be divided into three general sections: code to be run on the device,code to be run on the host,and the code related to the transfer of data between the host and the device.
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24
Threads are uniformly bundled in _________ .
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25
The dual warp scheduler will break up each thread block it is processing into _______ .
A)kernels
B)warps
C)grids
D)all of the above
A)kernels
B)warps
C)grids
D)all of the above
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26
The GPU has found its way into massively parallel programming environments for a wide range of applications,which is where the term __________ is derived from.
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27
A _________ is a bundle of 32 threads that start at the same starting address and their thread IDs are consecutive.
A)warp
B)grid
C)block
D)grouping
A)warp
B)grid
C)block
D)grouping
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28
The first NVIDIA GPU with added GPGPU support hardware was the _________ .
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29
The parallel code in the form of a function to be run on GPU is the ________ .
A)grid
B)thread
C)kernel
D)none of the above
A)grid
B)thread
C)kernel
D)none of the above
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30
The _________ performs transcendental operations,such as cosine,sine,reciprocal,and square root,in a single clock cycle.
A)SM
B)SIMD
C)SFU
D)FMA
A)SM
B)SIMD
C)SFU
D)FMA
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31
To enhance performance,a technique known as __________ is used for the shared L3 data cache.
A)cache banking
B)thread blocking
C)streaming
D)warping
A)cache banking
B)thread blocking
C)streaming
D)warping
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32
A subslice includes a unit called the _________,which is used for sampling texture and image surfaces.
A)stride
B)sampler
C)EU
D)floating-point
A)stride
B)sampler
C)EU
D)floating-point
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33
A _________ is a single instance of the kernel function.
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34
In 2006 NVIDIA facilitated the use of its new GPGPU language,________ .
A)GPU / GP
B)SIMD
C)CUDA
D)NVIDIA C
A)GPU / GP
B)SIMD
C)CUDA
D)NVIDIA C
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35
The EU can issue up to ________ different instructions simultaneously from different threads.
A)four
B)five
C)six
D)seven
A)four
B)five
C)six
D)seven
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36
__________ is a parallel computing platform and programming model created by NVIDIA and implemented by the GPUs that they produce.
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37
In the CPU the control logic and __________ make up the majority of the CPU's real estate.
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38
The number of blocks per kernel launch is called a __________ .
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39
__________ are caused by limited SFUs,double-precision multiplication,and branching.
A)Structural hazards
B)RAW data hazards
C)Vertical hazards
D)Latency hazards
A)Structural hazards
B)RAW data hazards
C)Vertical hazards
D)Latency hazards
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40
___________ is a GPU processing technology.
A)Fermi
B)Kepler
C)Maxwell
D)All of the above
A)Fermi
B)Kepler
C)Maxwell
D)All of the above
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41
The _________ GPU has a total of 16 SMs x 32 CUDA cores / SM,or 512 CUDA cores.
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42
A GPU uses a massively parallel ________ architecture to perform mainly mathematical operations.
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43
The _________ scheduler breaks up each thread block it is processing into warps.
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44
The _________ global scheduler unit on the GPU chip distributes the thread blocks to the SMs.
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45
The fundamental building block of the Gen8 architecture is the ________ unit.
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