Deck 15: Reduced Instruction Set Computers

Question 1

The Patterson study examined the dynamic behavior of _________ programs,independent of the underlying architecture.

A)HLL
B)RISC
C)CISC
D)all of the above

Answer 1

A

Question 2

To handle any possible pattern of calls and returns the number of register windows would have to be unbounded.

Answer 2

True

Question 3

The first commercial RISC product was _________.

A)SPARC
B)CISC
C)VAX
D)the Pyramid

Answer 3

D

Question 4

Unrolling can improve performance by increasing instruction parallelism by improving pipeline performance.

Question 5

The register file employs much shorter addresses than addresses for cache and memory.

Question 6

_________ is the fastest available storage device.

A)Main memory
B)Cache
C)Register storage
D)HLL

Question 7

Procedure calls and returns are not important aspects of HLL programs.

Question 8

_________ determines the control and pipeline organization.

A)Calculation
B)Execution sequencing
C)Operations performed
D)Operands used

Question 9

Pipelining is a means of introducing parallelism into the essentially sequential nature of a machine-instruction program.

Question 10

RISC processors are more responsive to interrupts because interrupts are checked between rather elementary operations.

Question 11

When using graph coloring,nodes that share the same color cannot be assigned to the same register.

Question 12

It is common for programs,both system and application,to continue to exhibit new bugs after years of operation.

Question 13

Almost all RISC instructions use simple register addressing.

Question 14

With simple,one cycle instructions,there is little or no need for microcode.

Question 15

The cache is capable of handling global as well as local variables.

Question 16

The major cost in the life cycle of a system is hardware.

Question 17

The register file is on the same chip as the ALU and control unit.

Question 18

_________ instructions are used to position quantities in registers temporarily for computational operations.

A)Load-and-store
B)Window
C)Complex
D)Branch

Question 19

Cache memory is a much faster memory than the register file.

Question 20

Microprogramming eases the task of designing and implementing the control unit and provides support for the family concept.

Question 21

Which stage is required for load and store operations?

A)I
B)E
C)D
D)all of the above

Question 22

The acronym CISC stands for _________.

Question 23

The R4000 can have as many as _______ instructions in the pipeline at the same time.

A)8
B)10
C)5
D)3

Question 24

The instruction location immediately following the delayed branch is referred to as the ________.

A)delay load
B)delay file
C)delay slot
D)delay register

Question 25

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.

A)write back
B)tag check
C)data cache
D)instruction execute

Question 26

A tactic similar to the delayed branch is the _________,which can be used on LOAD instructions.

A)delayed load
B)delayed program
C)delayed slot
D)delayed register

Question 27

Blocks of memory,recently used global variables,memory addressing,and one operand addressed and accessed per cycle are characteristics of _________ organizations.

Question 28

A ________ is defined to be the time it takes to fetch two operands from registers,perform an ALU operation,and store the result in a register.

Question 29

All MIPS R series processor instructions are encoded in a single ________ word format.

A)4-bit
B)8-bit
C)16-bit
D)32-bit

Question 30

Individual variables,compiler assigned global variables,register addressing,and multiple operands addressed and accessed in one cycle are characteristics of __________ organizations.

Question 31

Although a variety of different approaches to reduced instruction set architecture have been taken,certain characteristics are common to all of them: register-to-register operations,simple addressing modes,simple instruction formats,and __________.

Question 32

Introduced by IBM with its System / 360,the _________ is a set of computers offered with different price and performance characteristics that presents the same architecture to the user.

Question 33

A large number of general-purpose registers,and / or the use of compiler technology to optimize register usage,a limited and simple instruction set,and an emphasis on optimizing the instruction pipeline are all key elements of _________ architectures.

Question 34

The difference between the operations provided in high-level languages (HLLs)and those provided in computer architecture is known as the ________.

Question 35

A ________ instruction can be used to account for data and branch delays.

A)SUB
B)NOOP
C)JUMP
D)all of the above

Question 36

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses,registers,and the ALU.

A)16
B)32
C)64
D)128

Question 37

__________ is a way of increasing the efficiency of the pipeline by making use of a branch that does not take effect until after execution of the following instruction.

Question 38

The acronym RISC stands for __________.

Question 39

SPARC refers to an architecture defined by ________.

A)Microsoft
B)Apple
C)Sun Microsystems
D)IBM

Question 40

A _________ architecture is one that makes use of more,and more fine-grained pipeline stages.

A)parallel
B)superpipelined
C)superscalar
D)hybrid

Question 41

The MIPS R4000 processor chip is partitioned into two sections,one containing the CPU and the other containing a _________ for memory management.

Question 42

A ________ architecture replicates each of the pipeline stages so that two or more instructions at the same stage of the pipeline can be processed simultaneously.

Question 43

The work that has been done on assessing merits of the RISC approach can be grouped into two categories: quantitative and _________.

Question 44

The acronym SPARC stands for __________.

Question 45

________ can improve performance by reducing loop overhead,increasing instruction parallelism by improving pipeline performance,and improving register,data cache,or TLB locality.