Deck 16: Parallelism and Superscalar Processors

Question 1

The simplest instruction issue policy is to issue instructions in the exact order that would be achieved by sequential execution (in- order issue)and to write results in that same order (in-order completion).

Answer 1

True

Question 2

ARM architecture has yet to implement superscalar techniques in the instruction pipeline.

Answer 2

False

Question 3

Machine parallelism exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

Answer 3

False

Question 4

The situation where the second instruction needs data produced by the first instruction to execute is referred to as __________.

A)true data dependency
B)output dependency
C)procedural dependency
D)antidependency

Question 5

The superscalar approach can be used on __________ architecture.

A)RISC
B)CISC
C)neither RISC nor CISC
D)both RISC and CISC

Question 6

Which of the following is a fundamental limitation to parallelism with which the system must cope?

A)procedural dependency
B)resource conflicts
C)antidependency
D)all of the above

Question 7

In-order completion requires more complex instruction issue logic than out-of-order completion.

Question 8

The superscalar approach depends on the ability to execute multiple instructions in parallel.

Question 9

Register renaming eliminates antidependencies and output dependencies.

Question 10

The reorder buffer is temporary storage for results completed out of order that are then committed to the register file in program order.

Question 11

The instructions following a branch have a _________ on the branch and cannot be executed until the branch is executed.

A)resource dependency
B)procedural dependency
C)output dependency
D)true data dependency

Question 12

In effect,the Intel Core architecture implements a CISC instruction set architecture on a RISC microarchitecture.

Question 13

In the scalar organization there are multiple functional units,each of which is implemented as a pipeline and provides a degree of parallelism by virtue of its pipelined structure.

Question 14

The Cortex-A8 targets a wide variety of mobile and consumer applications including mobile phones,set-top boxes,gaming consoles and automotives navigation / entertainment systems.

Question 15

The schedulers are responsible for retrieving micro-ops from the micro-op queues and dispatching these for execution.

Question 16

In a traditional scalar organization there is a single pipelined functional unit for integer operations and one for floating-point operations.

Question 17

True data dependency is also called flow dependency or read after write (RAW)dependency.

Question 18

The superscalar approach has now become the standard method for implementing high-performance microprocessors.

Question 19

The essence of the ________ approach is the ability to execute instructions independently and concurrently in different pipelines.

A)scalar
B)branch
C)superscalar
D)flow dependency

Question 20

Resources include: memories,caches,buses,and register-file ports.

Question 21

Instead of the first instruction producing a value that the second instruction uses,with ___________ the second instruction destroys a value that the first instruction uses.

A)in-order issue
B)resource conflict
C)antidependency
D)out-of-order completion

Question 22

________ indicates whether this micro-op is scheduled for execution,has been dispatched for execution,or has completed execution and is ready for retirement.

A)State
B)Memory address
C)Micro-op
D)Alias register

Question 23

The term _________ parallelism refers to the degree to which,on average,the instructions of a program can be executed in parallel.

Question 24

The ________ protects critical data used by the operating system from user applications,separating processing tasks by disallowing access to each other's data,disabling access to memory regions,allowing memory regions to be defined as read-only,and detecting unexpected memory accesses that could potentially break the system.

Question 25

__________ exists when instructions in a sequence are independent and thus can be executed in parallel by overlapping.

A)Flow dependency
B)Instruction-level parallelism
C)Machine parallelism
D)Instruction issue

Question 26

_________ is determined by the number of instructions that can be fetched and executed at the same time and by the speed and sophistication of the mechanisms that the processor uses to find independent instructions.

A)Machine parallelism
B)Instruction-level parallelism
C)Output dependency
D)Procedural dependency

Question 27

In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.

Question 28

_________ is a measure of the ability of the processor to take advantage of instruction-level parallelism.

Question 29

Utilizing a branch target buffer (BTB),the _________ uses a dynamic branch prediction strategy based on the history of recent executions of branch instructions.

A)486
B)Pentium
C)Intel Core
D)Pentium Pro

Question 30

A _________ is a competition of two or more instructions for the same resource at the same time.

Question 31

The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.

Question 32

________ is used in scalar RISC processors to improve the performance of instructions that require multiple cycles.

A)In-order completion
B)In-order issue
C)Out-of-order completion
D)Out-of-order issue

Question 33

________ is a protocol used to issue instructions.

A)Micro-ops
B)Scalar
C)SIMD
D)Instruction issue policy

Question 34

________ refers to the process of initiating instruction execution in the processor's functional units.

A)Instruction issue
B)In-order issue
C)Out-of-order issue
D)Procedural issue

Question 35

Which of the following is a hardware technique that can be used in a superscalar processor to enhance performance?

A)duplication of resources
B)out-of-order issue
C)renaming
D)all of the above

Question 36

________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.

Question 37

The ________ introduced a full-blown superscalar design with out-of-order execution.

A)Pentium
B)Pentium Pro
C)386
D)486

Question 38

A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.

Question 39

Committing or _________ the instruction is when instructions are conceptually put back into sequential order and their results are recorded.

Question 40

The _________ predicts the instruction stream,fetches instructions from the L1 instruction cache,and places the fetched instructions into a buffer for consumption by the decode pipeline.

Question 41

The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.

Question 42

Instruction-level parallelism is also determined by __________,which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.

Question 43

With ____________ any number of instructions may be in the execution stage at any one time,up to the maximum degree of machine parallelism across all functional units.

Question 44

An alternative to _________ is a scoreboarding.

Question 45

Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion,out-of-order issue with out-of-order completion,and ____________.