The Essentials Of Computer Organization And Architecture 4th Edition by Linda Null,Julia Lobur

Exercise 57

Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program.
Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown here:
The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. The memory addresses of the first four accesses have been loaded into the cache blocks as shown below. (The contents of the tag are shown in binary, and the cache "contents" are simply the address stored at that cache location.)
a) What is the hit ratio for the entire memory reference sequence given above, assuming that we count the first four accesses as misses?
b) What memory blocks will be in the cache after the last address has been accessed?