Deck 1: Computer Architecture and Register Transfer Language FAQS

Question 1

RTL stands for:

A)Random transfer language
B)Register transfer language
C)Arithmetic transfer language
D)All of these

Answer 1

Register transfer language

Question 2

Which operations are used for addition, subtraction, increment, decrement and complement function:

A)Bus
B)Memory transfer
C)Arithmetic operation
D)All of these

Answer 2

All of these

Question 3

The method of writing symbol to indicate a provided computational process is called as a:

A)Programming language
B)Random transfer language
C)Register transfer language
D)Arithmetic transfer language

Answer 3

Programming language

Question 4

Which language is termed as the symbolic depiction used for indicating the series:

A)Random transfer language
B)Register transfer language
C)Arithmetic transfer language
D)All of these

Question 5

The register that includes the address of the memory unit is termed as the :

A)MAR
B)PC
C)IR
D)None of these

Question 6

In register transfer the processor register as:

A)MAR
B)PC
C)IR
D)RI

Question 7

How many types of micro operations:

A)2
B)4
C)6
D)8

Question 8

Which are the operation that a computer performs on data that put in register:

A)Register transfer
B)Arithmetic
C)Logical
D)All of these

Question 9

In memory read the operation puts memory address on to a register known as :

A)PC
B)ALU
C)MR
D)All of these

Question 10

Which operation puts memory address in memory address register and data in DR:

A)Memory read
B)Memory Write
C)Both
D)None

Question 11

In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is _________  

A)EA = 5+R1
B)EA = R1
C)EA = [R1]
D)EA = 5+[R1]

Question 12

The addressing mode which makes use of in-direction pointers is _________  

A)Indirect addressing mode
B)Index addressing mode
C)Relative addressing mode
D)Offset addressing mode

Question 13

_________addressing mode is most suitable to change the normal sequence of execution of instructions.

A)Relative
B)Indirect
C)Index with Offset
D)Immediate

Question 14

The effective address of the following instruction is MUL 5(R1,R2).

A)5+R1+R2
B)5+(R1*R2)
C)5+[R1]+[R2]
D)5*([R1]+[R2])

Question 15

The addressing mode, where you directly specify the operand value is _________    

A)Immediate
B)Direct
C)Definite
D)Relative

Question 16

Which of the following register is used in the control unit of the CPU to indicate the next instruction which is to be executed ?

A)Accumulator
B)Index register
C)Instruction decoder
D)Program counter

Question 17

If a processor does not have any stack pointer register, then

A)It cannot have subroutine call instruction
B)It can have subroutine call instruction, but no nested subroutine
C)Nested subroutine calls are possible, but interrupts are not
D)All sequences of subroutine calls and also interrupts are

Question 18

The Sun micro systems processors usually follow _________architecture.

A)CISC
B)ISA
C)ULTRA SPARC
D)RISC

Question 19

Which of the architecture is power efficient?

A)CISC
B)RISC
C)ISA
D)IANA

Question 20

The master indicates that the address is loaded onto the BUS, by activating signal.

A)MSYN
B)SSYN
C)WMFC
D)INTR

Question 21

In IBM's S360/370 systems lines are used to select the I/O devices.

A)SCAN in and out
B)Connect
C)Search
D)Peripheral

Question 22

The transmission on the asynchronous BUS is also called _________

A)Switch mode transmission
B)Variable transfer
C)Bulk transfer
D)Hand-Shake transmission

Question 23

The BUS that allows I/O, memory and Processor to coexist is _________    

A)Attributed BUS
B)Processor BUS
C)Backplane BUS
D)External BUS

Question 24

The chip can be disabled or cut off from an external connection using _________  

A)Chip select
B)LOCK
C)ACPT
D)RESET

Question 25

The less space consideration as lead to the development of (for large memories).

A)SIMM's
B)DIMS's
C)SRAM's
D)Both SIMM's and DIMS's