Deck 8: Understanding Flip-Flop and Sequential Circuits

Question 1

One example of the use of an S-R flip-flop is as

A)transition pulse generator
B)racer
C)switch debouncer
D)astable oscillator

Answer 1

switch debouncer

Question 2

The truth table for an S-R flip-flop has how many VALID entries?

A)1
B)2
C)3
D)4

Answer 2

3

Question 3

When both inputs of a J-K flip-flop cycle, the output will______________      

A)be invalid
B)change
C)not change
D)toggle

Answer 3

not change

Question 4

Which of the following is correct for a gated D-type flip-flop?

A)the q output is either set or reset as soon as the d input goes high or low
B)the output complement follows the input when enabled
C)only one of the inputs can be high at a time
D)the output toggles if one of the inputs is held high

Question 5

A basic S-R flip-flop can be constructed by cross- coupling of which basic logic gates?

A)and or or gates
B)xor or xnor gates
C)nor or nand gates
D)and or nor gates

Question 6

Whose operations are more faster among the following?

A)combinational circuits
B)sequential circuits
C)latches
D)flip-flops

Question 7

How many types of sequential circuits are?

A)2
B)3
C)4
D)5

Question 8

The sequential circuit is also called______________      

A)flip-flop
B)latch
C)strobe
D)adder

Question 9

The basic latch consists of______________      

A)two inverters
B)two comparators
C)two amplifiers
D)two adders

Question 10

In S-R flip-flop, if Q = 0 the output is said to be

A)set
B)reset
C)previous state
D)current state

Question 11

The output of latches will remain in set/reset untill

A)the trigger pulse is given to change the state
B)any pulse given to go into previous state
C)they don't get any pulse more
D)the pulse is edge-triggered

Question 12

What is a trigger pulse?

A)a pulse that starts a cycle of operation
B)a pulse that reverses the cycle of operation
C)a pulse that prevents a cycle of operation
D)a pulse that enhances a cycle of operation

Question 13

The circuits of NOR based S-R latch classified as asynchronous sequential circuits, why?

A)because of inverted outputs
B)because of triggering functionality
C)because of cross-coupled connection
D)because of inverted outputs & triggering functionality

Question 14

A latch is an example of a______________      

A)monostable multivibrator
B)astable multivibrator
C)bistable multivibrator
D)555 timer

Question 15

Latch is a device with______________      

A)one stable state
B)two stable state
C)three stable state
D)infinite stable states

Question 16

Why latches are called a memory devices?

A)it has capability to stare 8 bits of data
B)it has internal memory of 4 bit
C)it can store one bit of data
D)it can store infinite amount of data

Question 17

Two stable states of latches are______________      

A)astable & monostable
B)low input & high output
C)high output & low output
D)low output & high input

Question 18

The full form of SR is______________      

A)system rated
B)set reset
C)set ready
D)set rated

Question 19

The SR latch consists of______________      

A)1 input
B)2 inputs
C)3 inputs
D)4 inputs

Question 20

The outputs of SR latch are______________      

A)x and y
B)a and b
C)s and r
D)q and q'

Question 21

The NAND latch works when both inputs are

A)1
B)0
C)inverted
D)don't cares

Question 22

The first step of analysis procedure of SR latch is to______________      

A)label inputs
B)label outputs
C)label states
D)label tables

Question 23

The inputs of SR latch are______________      

A)x and y
B)a and b
C)s and r
D)j and k

Question 24

When a high is applied to the Set line of an SR latch, then______________      

A)q output goes high
B)q' output goes high
C)q output goes low
D)both q and q' go high

Question 25

When both inputs of SR latches are low, the latch

A)q output goes high
B)q' output goes high
C)it remains in its previously set or reset state
D)it goes to its next set or reset state