Deck 13: Programmable Logic Device Architectures

Question 1

The output line of an AND gate in a Programmable Logic Device is normally called a:

A) fusible link line.
B) product line.
C) programmable line.
D) logic line.

Answer 1

product line.

Question 2

Which of the following best describes PLD PROM architecture?

A) The inputs to the AND array and the product line inputs to the OR gates are both programmable.
B) The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable.
C) The inputs to the AND array and the product line inputs to the OR gates are both hard- wired.
D) The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired.

Answer 2

The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable.

Question 3

What does an x represent on a PLD diagram?

A) An intact fuse
B) A hard- wired connection
C) A nonprogrammable connection
D) A "don't care" condition

Answer 3

An intact fuse

Question 4

Which of the following best describes typical PAL architecture?

A) The inputs to the AND array and the product line inputs to the OR gates are both hard- wired.
B) The inputs to the AND array are programmable and the product line inputs to the OR gates are hard- wired.
C) The inputs to the AND array and the product line inputs to the OR gates are both programmable.
D) The inputs to the AND array are hard- wired and the product line inputs to the OR gates are programmable.

Question 5

Which of the following have a programmable OR array and a programmable AND array?

A) PAL
B) PROM
C) PLA
D) both B and C

Question 6

For a given PLD, if none of the input to the OR gate are connected, the output of this gate will be:

A) invalid.
B) tri- state.
C) LOW.
D) HIGH.

Question 7

A blown input to an AND gate in a PLD would normally be held:

A) tri- state.
B) LOW.
C) invalid.
D) HIGH.

Question 8

The "dot" in a PLD diagram represents:

A) an open connection.
B) a programmable point.
C) a hard- wired connection.
D) an intact fuse.

Question 9

Which of the following PLDs has two programmable arrays?

A) GAL
B) PROM
C) FPLA
D) PAL

Question 10

The basic difference between a PROM and a PAL is that:

A) in PAL, inputs to its AND array are programmable, whereas the OR inputs are not.
B) in PAL, inputs to its XOR array are not programmable, whereas they are in PROM.
C) in PAL, inputs to its AND array are not programmed whereas the OR inputs are.
D) Both A and B are true.

Question 11

Which of the following refers to a PAL that has eight registered outputs plus eight dedicated inputs?

A) PAL16V8
B) PAL16R8
C) PAL16DFF8
D) PAL16L8

Question 12

Which of the following contains an EEPROM array?

A) GAL
B) PROM
C) FPLA
D) PAL

Question 13

GAL devices are very similar to what type of devices?

A) PROM
B) PLD
C) PAL
D) SPLD

Question 14

The GAL devices use _______to select input terms.

A) Fuse links
B) EEPROM memory
C) Matrix links
D) ROM

Question 15

What advantage do GAL devices have over PAL devices other than the ability to be reprogrammed?

A) The output macrocell
B) AND/OR arrays
C) They are cheaper
D) PIAs

Question 16

In the variable DECODE.OE the OE is a(n):

A) extension.
B) variable name.
C) expression.
D) state name.

Question 17

A PLD is an IC that contains large numbers of gates, FFs, and registers that are often interconnected by fusible links.

Question 18

Universal programmers can program any type of device EXCEPT EPROMS.

Question 19

Low level development tools often accept truth tables as input.

Question 20

The first step in the development cycle results in the labeling of all inputs and outputs.

Question 21

A FPGA is an array of PLD cells.

Question 22

The term ASICS is often used to describe simple PLDs.

Question 23

Many PLD's include a programmable output____ feature that gives the designer the option to invert any of the device outputs.

Question 24

PLD's are programmed by_____ fuses.

Question 25

A PC, running developmental software, translates an input design into a file called a fuse_______ .

Question 26

Most PLD programmers use a_____socket to hold the device.

Question 27

The four input- only pins found on MAX7000s devices can be configured as general user inputs or as______.

Question 28

In the MAX7000s family, the number of I/O pins is determined by ______.

Question 29

GALs contain optional flip- flops for______.

Question 30

Software development packages can be classified as either ____ level development systems or______ level logic compilers.

Question 31

The major difference in architecture between MAX7000s devices and MAX II devices is_______

Question 32

When writing the logic equations in PLD development software the logic_____is placed on the right side.

Question 33

In the MAX II family, the LUTs typically handle _____ input variables.

Question 34

Whenever a MAX II device is powered up, it is necessary to load the LUT memory for the desired functions. This is because the SRAM is____ .

Question 35

A fuse _____ file shows the actual fuse pattern that will be burned into the PLD.

Question 36

MAX II architecture has 10 logic elements arranged together into a_____

Question 37

The major structures in the MAX7000s are the LABs and the_____.

Question 38

Each MAX II device contains CFM and UFM. These are_____.

Question 39

When writing the logic equations in PLD development software the_____ is placed on the left side.

Question 40

Compared to the Cyclone II the Cyclone III has _____performance and_____cost.

Question 41

In the MAX II series, _____provide clock frequency multiplication and division.