Caching. "One of the keys to happiness is a bad memory." -Rita Mae Brown Consider the following piece of code:
int x = 0, y = 0; // The compiler puts x in r1 and y in r2. int i; // The compiler put i in r3.
int A[4096]; // A is in memory at address 0x10000
...
for (i=0;i

Question

Caching. "One of the keys to happiness is a bad memory." -Rita Mae Brown Consider the following piece of code:
int x = 0, y = 0; // The compiler puts x in r1 and y in r2. int i; // The compiler put i in r3.
int A[4096]; // A is in memory at address 0x10000
...
for (i=0;i<1024;i++) { x += A[i];
}
for (i=0;i<1024;i++) { y += A[i+2048];
}
(a) Assume that the system has a 8192-byte, direct-mapped data cache with 16-byte blocks. Assuming that the cache starts out empty, what is the series of data cache hits and misses for this snippet of code. Assume that ints are 32-bits.
(b) Assume that an iteration of a loop in which the load hits takes 10 cycles but that an iteration of a loop in which the load misses takes 100 cycles. What is the execution time of this snippet with the aforementioned cache?
(c) Repeat part A except assume that the cache is 2-way set associative with an LRU replacement policy and 16-byte sets (8-byte blocks).
(d) Repeat part B using the cache described in part C. Is the direct-mapped or the set-associative cache better?

Quizplus · Accepted Answer

The Answer of Caching. "One of the keys to happiness is a bad memory." -Rita Mae Brown Consider the following piece of code:
int x = 0, y = 0; // The compiler puts x in r1 and y in r2. int i; // The compiler put i in r3.
int A[4096]; // A is in memory at address 0x10000
...
for (i=0;i<1024;i++) { x += A[i];
}
for (i=0;i<1024;i++) { y += A[i+2048];
}
(a) Assume that the system has a 8192-byte, direct-mapped data cache with 16-byte blocks. Assuming that the cache starts out empty, what is the series of data cache hits and misses for this snippet of code. Assume that ints are 32-bits.
(b) Assume that an iteration of a loop in which the load hits takes 10 cycles but that an iteration of a loop in which the load misses takes 100 cycles. What is the execution time of this snippet with the aforementioned cache?
(c) Repeat part A except assume that the cache is 2-way set associative with an LRU replacement policy and 16-byte sets (8-byte blocks).
(d) Repeat part B using the cache described in part C. Is the direct-mapped or the set-associative cache better?

Caching "One of the Keys to Happiness Is a Bad