The output of an OR gate is connected directly to the input of an AND gate. The other AND gate input is a constant "Enable" HIGH. A technician checks the inputs to the OR gate and notes a HIGH and LOW. The output of the OR gate is noted as being a HIGH. The "Enable" HIGH input to the AND gate is verified as normal. The technician checks the OR gate input to the AND gate and observes a LOW or no voltage condition. Of the probable causes listed, select the one that most likely is the problem. Assume CMOS gates.
A) A short between the OR gate output and the AND gate input
B) An internal short in the AND gate
C) An open connection between the OR gate output and the AND gate input
D) A short between the input terminals of the AND gate

Question

Quizplus · Accepted Answer

Given the scenario, the most likely issue is an open connection between the OR gate output and the AND gate input. This would explain why the OR gate's output is HIGH (due to one HIGH input), but the AND gate does not receive this HIGH signal, showing a LOW or no voltage condition instead.

The Output of an OR Gate Is Connected Directly to the Input