Signal state is held constant in a clock cycle ________.
A) for energy efficiency
B) to make it easier for the receiver to sample the state
C) to emphasize differences between clock cycles
D) none of the above

Question

Quizplus · Accepted Answer

Holding the signal state constant in a clock cycle makes it easier for the receiver to sample the state at the correct time. This is because the receiver only needs to measure the state once per clock cycle, rather than having to distinguish between multiple states within a clock cycle. It may also lead to some energy efficiency improvements, but that is not the primary reason for holding the signal state constant. Additionally, it doesn't necessarily emphasize differences between clock cycles.

Signal State Is Held Constant in a Clock Cycle ________