Figure 3 Assume I DSS = 3.5 mA and V GS(off) = -2 V.
-Refer to Figure 3. An advantage to the voltage divider bias over self- bias is that voltage- divider bias
A)allows for greater variation in JFET parameters
B)has higher input resistance
C)enables the gate- source to be forward- biased or reverse- biased
D)all of the above

Question

Figure 3 Assume I DSS = 3.5 mA and V GS(off) = -2 V.
-Refer to Figure 3. An advantage to the voltage divider bias over self- bias is that voltage- divider bias
A)allows for greater variation in JFET parameters 
B)has higher input resistance 
C)enables the gate- source to be forward- biased or reverse- biased 
D)all of the above

Quizplus · Accepted Answer

Voltage divider bias allows for greater variation in JFET parameters because it stabilizes the operating point against variations in transistor parameters.

Figure 3 Assume IDSS = 3

Figure 3 Assume I_DSS= 3