Question 1

Design a 8-way set associative cache that has 16 blocks and 32 bytes per block. Assume a 32 bit address. Calculate the following:
(a) How many bits are used for the byte offset?
(b) How many bits are used for the set (index) field?
(c) How many bits are used for the tag?

Accepted Answer

5 bits ,2 bits
25 bits

Question 2

For a data cache with a 92% hit rate and a 2-cycle hit latency, calculate the average memory access latency. Assume that latency to memory and the cache miss penalty together is 124 cycles. Note: The cache must be accessed after memory returns the data.

Accepted Answer

AMAT = 2 + 0.08*124
= 11.92 cycles
(Part C)

Question 3

Both DRAM and SRAM must be refreshed periodically using a dummy read/write operation.

Accepted Answer

SRAM (Static RAM) does not need to be refreshed periodically because it uses bistable latching circuitry to maintain the data as long as power is supplied. DRAM (Dynamic RAM), on the other hand, requires periodic refreshing to maintain the data stored in its capacitors.

Question 4

A virtual cache access time is always faster than that of a physical cache?

Accepted Answer

The answer of A virtual cache access time is always...

Question 5

This question covers virtual memory access. Assume a 5-bit virtual address and a memory system that uses 4 bytes per page. The physical memory has 16 bytes (four page frames). The page table used is a one-level scheme that can be found in memory at the PTBR location. Initially the table indicates that no virtual pages have been mapped. Implementing a LRU page replacement algorithm, show the contents of physical memory after the following virtual accesses: 10100, 01000, 00011, 01011, 01011,11111. Show the contents of memory and the page table information after each access successfully completes in figures that follow. Also indicate when a page fault occurs. Each page table entry (PTE) is 1 byte.

Accepted Answer

The answer of This question covers virtual memory access. Assume...

Question 6

Memory interleaving is a technique for reducing memory access time through increased bandwidth utilization of the data bus.

Accepted Answer

Memory interleaving allows multiple memory modules to be accessed simultaneously, increasing the amount of data that can be transferred over the data bus at any given time. This reduces overall memory access time and increases the bandwidth utilization of the data bus.

Question 7

Caches and Address Translation. Consider a 64-byte cache with 8 byte blocks, an associativity of 2 and LRU block replacement. Virtual addresses are 16 bits. The cache is physically tagged. The processor has 16KB of physical memory.
(a) What is the total number of tag bits?
(b) Assuming there are no special provisions for avoiding synonyms, what is the minimum page size?
(c) Assume each page is 64 bytes. How large would a single-level page table be given that each page requires 4 protection bits, and entries must be an integral number of bytes.
(d) For the following sequence of references, label the cache misses.Also, label each miss as being either a compulsory miss, a capacity miss, or a conflict miss. The addresses are given in octal (each digit represents 3 bits). Assume the cache initially contains block addresses: 000, 010, 020, 030, 040, 050, 060, and 070 which were accessed in that order
   (e) Which of the following techniques are aimed at reducing the cost of a miss: dividing the current block into sub-blocks, a larger block size, the addition of a second level cache, the addition of a victim buffer, early restart with critical word first, a writeback buffer, skewed associativity, software prefetching, the use of a TLB, and multi-porting.
(f) Why are the first level caches usually split (instructions and data are in different caches) while the L2 is usually unified (instructions and data are both in the same cache)?

Accepted Answer

The answer of Caches and Address Translation. Consider a 64-byte...

Question 8

A two part question
(a) Why is miss rate not a good metric for evaluating cache performance? What is the appropriate metric? Give its definition. What is the reason for using a combination of first and second- level caches rather than using the same chip area for a larger first-level cache?
(b) The original motivation for using virtual memory was "compatibility". What does that mean in this context? What are two other motivations for using virtual memory?

Accepted Answer

The answer of A two part question
(a) Why is miss...

Question 9

The memory architecture of a machine X is summarized in the following table.
  (a) Assume that there are 8 bits reserved for the operating system functions (protection, replacement, valid, modified, and Hit/Miss- All overhead bits) other than required by the hardware translation algorithm. Derive the largest physical memory size (in bytes) allowed by this PTE format. Make sure you consider all the fields required by the translation algorithm.
(b) How large (in bytes) is the page table?
(c) Assuming 1 application exists in the system and the maximum physical memory is devoted to the process, how much physical space (in bytes) is there for the application's data and code.

Accepted Answer

The answer of The memory architecture of a machine X...

Question 10

What needs to be stored in a branch target buffer in order to eliminate the branch penalty for an unconditional branch?
(a) Address of branch target
(b) Address of branch target and branch prediction
(c) Instruction at branch target.

Accepted Answer

The answer of What needs to be stored in a...

Question 11

A write-through cache typically requires less bus bandwidth than a write-back cache.

Accepted Answer

A write-through cache writes data to both the cache and the backing store simultaneously, leading to more immediate bus traffic compared to a write-back cache, which only writes data to the backing store when it is replaced or modified in the cache, potentially reducing bus bandwidth usage.

Question 12

The Average Memory Access Time equation (AMAT) has three components: hit time, miss rate, and miss penalty. For each of the following cache optimizations, indicate which component of the AMAT equation is improved.
$\bullet$Using a second-level cache
$\bullet$Using a direct-mapped cache
$\bullet$Using a 4-way set-associative cache
$\bullet$Using a virtually-addressed cache
$\bullet$Performing hardware pre-fetching using stream buffers
$\bullet$Using a non-blocking cache
$\bullet$Using larger blocks

Accepted Answer

The answer of The Average Memory Access Time equation (AMAT)...

Question 13

a. What are the two characteristics of program memory accesses that caches exploit?
b. What are three types of cache misses?
c. Design a 128KB direct-mapped data cache that uses a 32-bit address and 16 bytes per block. Calculate the following: (a)How many bits are used for the byte offset?
(b)How many bits are used for the set (index) field? (c) How many bits are used for the tag?

Accepted Answer

The answer of a. What are the two characteristics of...

Question 14

In what pipeline stage is the branch target buffer checked?
(a) Fetch
(b) Decode
(c) Execute
(d) Resolve

Accepted Answer

The answer of In what pipeline stage is the branch...

Question 15

Cache performance is of less importance in faster processors because the processor speed compensates for the high memory access time.

Accepted Answer

Cache performance becomes even more important in faster processors as the speed difference between the processor and memory increases, making the memory access time relatively slower. Faster processors may have larger caches or smarter caching algorithms to improve performance.

Question 16

Calculate the performance of a processor taking into account stalls due to data cache and instruction cache misses. The data cache (for loads and stores) is the same as described in Part B and 30% of instructions are loads and stores. The instruction cache has a hit rate of 90% with a miss penalty of 50 cycles. Assume the base CPI using a perfect memory system is 1.0. Calculate the CPI of the pipeline, assuming everything else is working perfectly. Assume the load never stalls a dependent instruction and assume the processor must wait for stores to finish when they miss the cache. Finally, assume that instruction cache misses and data cache misses never occur at the same time. Show your work.
· Calculate the additional CPI due to the icache stalls.
· Calculate the additional CPI due to the dcache stalls.
· Calculate the overall CPI for the machine.

Accepted Answer

The answer of Calculate the performance of a processor taking...

Question 17

Write the formula for the average memory access time assuming one level of cache memory:

Accepted Answer

The answer of Write the formula for the average memory...

Question 18

High associativity in a cache reduces compulsory misses.

Accepted Answer

Compulsory misses are caused by the first access to a block that has never been in the cache before, and this is independent of the cache's associativity. Associativity mainly affects conflict and capacity misses.

Question 19

B. Derive the hit ratio for the access sequence in Part A.

Accepted Answer

The answer of   B. Derive the hit ratio...

Question 20

A processor has a 32 byte memory and an 8 byte direct-mapped cache. Table 0 shows the current state of the cache. Write hit or miss under the each address in the memory reference sequence below. Show the new state of the cache for each miss in a new table, label the table with the address, and circle the change:

Accepted Answer

The answer of A processor has a 32 byte memory...

Quiz 5: Large and Fast

Design a 8-way set associative cache that has 16 blocks and 32 bytes per block. Assume a 32 bit address. Calculate the following: (a) How many bits are used for the byte offset? (b) How many bits are used for the set (index) field? (c) How many bits are used for the tag?