This Is a Three-Part Question About Critical Path Calculation $\bullet$ Given the Data Path Latencies Above, Which Instruction Determines the a Simple

This is a three-part question about critical path calculation. Consider a simple single- cycle implementation of MIPS ISA. The operation times for the major functional components for this machine are as follows:
- Below is a copy of the MIPS single-cycle datapath design. In this implementation the clock cycle is determined by the longest possible path in the machine. The critical paths for the different instruction types that need to be considered are: R-format, Load-word, and store-word. All instructions have the same instruction fetch and decode steps. The basic register transfer of the instructions are:
Fetch/Decode: Instruction <- IMEM[PC];
R-type: R[rd] <- R[rs] op R[rt]; PC <- PC + 4;
load: R[rt] <- DMEM[ R[rs] + signext(offset)]; PC <- PC +4; store: DMEM[ R[rs] + signext(offset)] <- R[Rt]; PC <- PC +4;
(Part C)
Use the total latency column to derive the following critical path information:
$\bullet$ Given the data path latencies above, which instruction determines the overall machine critical path (latency)?
$\bullet$ What will be the resultant clock cycle time of the machine based on the critical path instruction?
$\bullet$ What frequency will the machine run?