Question 1

Figure 7.1.1
The NMOS transistor in the circuit in Fig. 7.1.1 has $\mu_{n} C_{o x}=0.4 \mathrm{~mA} / \mathrm{V}^{2}, W / L=25$, and $V_{t}=$ $0.4 \mathrm{~V}$
(a) Find the value of $V_{G S}$ that results in saturationmode operation with a dc current of $0.1 \mathrm{~mA}$. Neglect the Early effect.
(b) Find the value of $R_{D}$ that results in a dc drain voltage of $0.5 \mathrm{~V}$.
(c) Find $g_{m}$ and $r_{O}$ at the dc operating point specified above. Assume $V_{A}=5 \mathrm{~V}$.
(d) Find the open-circuit voltage gain $A_{v o}$.
(e) If a sinusoidal signal with peak amplitude $V_{i}$ is superimposed on the dc voltage $V_{G S}$, find the maximum allowable value of $V_{i}$ for which the transistor operates in saturation.

Accepted Answer

(a)

Figure 7.1.1
$$\begin{aligned}
I_{D} & =\frac{1}{2}\left(\mu_{n} C_{O x}\right)(W / L)\left(V_{G S}-V_{t}\right)^{2} \
0.1
 & =\frac{1}{2} \times 0.4 \times 25\left(V_{G S}-0.4\right)^{2} \
\Rightarrow V_{G S} & =0.541 \mathrm{~V}
\end{aligned}$$
(b)
$$R_{D}=\frac{1.5-V_{D}}{I_{D}}=\frac{1.5-0.5}{0.1}=10 \mathrm{k} \Omega$$
(c)
$$g_{m}=\frac{2 I_{D}}{V_{O V}}$$
where
$$\begin{aligned}
V_{O V} & =V_{G S}-V_{t}=0.541-0.4=0.141 \mathrm{~V} \
g_{m} & =\frac{2 \times 0.1}{0.141}=1.42 \mathrm{~mA} / \mathrm{V} \
r_{o} & =\frac{V_{A}}{I_{D}}=\frac{5}{0.1}=50 \mathrm{k} \Omega
\end{aligned}$$
(d)
$$\begin{aligned}
A_{v o} & =-g_{m}\left(R_{D} \| r_{o}\right) \
& =-1.42(10 \| 50) \
& =-11.8 \mathrm{~V} / \mathrm{V}
\end{aligned}$$
(e) At the edge of saturation,
$$v_{G \max }-v_{D \min }=V_{t}$$
Here,
$$\begin{aligned}
v_{G \max } & =V_{G S}+\hat{V}_{i}=0.541+\hat{V}_{i} \
v_{D \min } & =V_{D}-\left|A_{v o}\right| \hat{V}_{i} \
& =0.5-11.8 \hat{V}_{i}
\end{aligned}$$
Thus,
$$\begin{gathered}
0.541
+\hat{V}_{i}-0.5+11.8 \hat{V}_{i}=0.4 \
\Rightarrow \hat{V}_{i}=28 \mathrm{mV}
\end{gathered}$$

Question 2

An NMOS transistor fabricated in a $0.18-\mu \mathrm{m}$ CMOS technology has $L=0.54 \mu \mathrm{m}$ and $W=$ $10.8 \mu \mathrm{m}$. The technology is specified to have $\mu_{n} C_{o x}=400 \mu \mathrm{A} / \mathrm{V}^{2}, V_{t n}=0.5 \mathrm{~V}$, and $V_{A}^{\prime}=$ $5 \mathrm{~V} / \mu \mathrm{m}$.
(a) If the device is operated in saturation with an overdrive voltage of $0.2 \mathrm{~V}$, find the required values of $I_{D}$ and $V_{G S}$, along with the resulting values of $g_{m}$ and $r_{o}$. (b) If the gate width is doubled but the value of $V_{O V}$ is maintained, what do the values of $I_{D}, g_{m}$, and $r_{o}$ become?

Accepted Answer

(a) Saturation with $V_{O V}=0.2 \mathrm{~V}$,
$$\begin{aligned}
I_{D} & =\frac{1}{2}\left(\mu_{n} C_{O x}\right)(W / L) V_{O V}^{2} \
& =\frac{1}{2} \times 0.4 \times(10.8 / 0.54) \times 0.2^{2} \
& =0.16 \mathrm{~mA} \
V_{G S} & =V_{t n}+V_{O V}=0.5+0.2=0.7 \mathrm{~V}
\end{aligned}$$
$$\begin{aligned}
g_{m} & =\frac{2 I_{D}}{V_{O V}}=\frac{2 \times 0.16}{0.2}=1.6 \mathrm{~mA} / \mathrm{V} \
r_{o} & =\frac{V_{A}}{I_{D}}=\frac{V_{A}^{\prime} L}{I_{D}}=\frac{5 \times 0.54}{0.16}=16.9 \mathrm{k} \Omega
\end{aligned}$$
(b) If $W$ is doubled while $V_{O V}$ is maintained, we see from Eq. (1) that $I_{D}$ doubles to
$$I_{D}=0.32 \mathrm{~mA}$$
From
$$g_{m}=\frac{2 I_{D}}{V_{O V}}$$
we see that $g_{m}$ doubles to
$$g_{m}=3.2 \mathrm{~mA} / \mathrm{V}$$
Finally, from
$$r_{o}=\frac{V_{A}}{I_{D}}$$
we see that $r_{O}$ is halved to
$$r_{o}=8.45 \mathrm{k} \Omega$$

Question 3

A $0.18-\mu \mathrm{m}$ CMOS technology is specified to have $\mu_{n}=450 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, \mu_{p}=100 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, C_{o x}=$ $8.6 \mathrm{fF} / \mu \mathrm{m}^{2}, V_{t n}=-V_{t p}=0.5 \mathrm{~V}$, and dc power supply of $1.8 \mathrm{~V}$.
(a) Find the transconductance parameters $k_{n}^{\prime}$ and $k_{p}^{\prime}$ expressed in $\mu \mathrm{A} / \mathrm{V}^{2}$.
(b) Find the $W / L$ ratios of matched NMOS and PMOS transistors that exhibit resistance $r_{D S}$ of $250 \Omega$ when operated in the triode region with an overdrive voltage of $0.3 \mathrm{~V}$. If twice-theminimum channel length is used, specify the width of the NMOS transistor and the PMOS transistor.
(c) If the devices in (b) are operated in saturation with $\left|V_{O V}\right|=0.2 \mathrm{~V}$, what drain current results? If for each transistor the source is connected to ground, what should the gate voltages be? In each case, specify the range of voltages permitted at the drain for saturation-mode operation to be maintained.
(d) If the drain currents in (c) are to be reduced by a factor of 4 , what should the overdrive voltage be? If instead of changing $\left|V_{O V}\right|$, the IC designer redesigns the widths of the transistors, what $W$ values would be required?
(e) If the devices described in (b) above are operated in saturation with $\left|V_{O V}\right|=0.2 \mathrm{~V}$, find the resulting value of $g_{m}$.
(f) If an NMOS transistor as in (e) above is connected as a common-source amplifier with $R_{D}=$ $5 \mathrm{k} \Omega$ and $V_{D D}=1.8 \mathrm{~V}$, what dc voltage would appear at the drain? What small-signal voltage gain $A_{v}$ would be obtained?
(g) Recalculate the voltage gain in (f) taking into account channel-length modulation. Assume the
Early voltage for the process technology is specified as $10 \mathrm{~V} / \mu \mathrm{m}$.

Accepted Answer

(a)
$$\begin{aligned}
k_{n}^{\prime} & =\mu_{n} C_{o x} \
& =450 \frac{\mathrm{cm}^{2}}{\mathrm{~V} \cdot \mathrm{s}} \times 8.6 \times 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \
& =450 \times 10^{8} \frac{\mu \mathrm{m}^{2}}{\mathrm{~V} \cdot \mathrm{s}} \times 8.6 \times 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \
& =387 \times 10^{-6} \frac{\mathrm{F}}{\mathrm{V} \cdot \mathrm{s}} \
& =387 \mu \mathrm{A} / \mathrm{V}^{2} \
k_{p}^{\prime} & =k_{n}^{\prime} \times \frac{\mu_{p}}{\mu_{n}}=387 \times \frac{100}{450} \
& =86 \mu \mathrm{A} / \mathrm{V}^{2}
\end{aligned}$$
(b) For an NMOS transistor operating in a triode region,
$$\begin{aligned}
r_{D S} & =\frac{1}{k_{n}^{\prime}(W / L)_{N} V_{O V}} \
250 & =\frac{1}{387 \times 10^{-6} \times(W / L)_{N} \times 0.3} \
\Rightarrow(W / L)_{N} & =34.5
\end{aligned}$$
For a matched PMOS transistor,
$$\begin{aligned}
(W / L)_{P} & =(W / L)_{N} \times \frac{k_{n}^{\prime}}{k_{p}^{\prime}} \
& =34.5 \times \frac{387}{86}=155
\end{aligned}$$
Thus,
$$\begin{aligned}
L & =2 L_{\min }=2 \times 0.18=0.36 \mu \mathrm{m} \
W_{N} & =34.5 \times 0.36=12.4 \mu \mathrm{m} \
W_{P} & =155 \times 0.36=55.8 \mu \mathrm{m}
\end{aligned}$$
(c)
$$\begin{aligned}
I_{D P} & =I_{D N}=\frac{1}{2} k_{n}^{\prime}(W / L)_{N}\left|V_{O V}\right|^{2} \
& =\frac{1}{2} \times 387 \times 34.5 \times 0.2^{2} \
& =267 \mu \mathrm{A}
\end{aligned}$$
For the NMOS transistor,
$$V_{G}=V_{G S}=V_{t n}+V_{O V}=0.5+0.2=0.7 \mathrm{~V}$$
For the PMOS transistor,
  
Figure 7.3.1
From Fig. 7.3.1, we see that for the NMOS transistor to operate in saturation,
$$V_{D} \geq V_{O V}$$
that is,
$$V_{D} \geq 0.2 \mathrm{~V}$$
For the PMOS transistor to operate in saturation,
$$V_{D} \leq-\left|V_{O V}\right|$$
that is,
$$V_{D} \leq-0.2 \mathrm{~V}$$
(d) Since $I_{D}$ is proportional to $\left|V_{O V}\right|^{2}$, the drain current can be reduced by a factor of 4 by reducing $\left|V_{O V}\right|$ by a factor of 2 , that is, to $0.1 \mathrm{~V}$. Alternatively, $\left|V_{O V}\right|$ can be kept constant and $W$ reduced by a factor of 4 , resulting in
$$W_{N}=\frac{34.5}{4}=8.63 \mu \mathrm{m}$$
and
$$W_{P}=\frac{155}{4}=38.8 \mu \mathrm{m}$$
(e)
$$g_{m}=\frac{2 I_{D}}{\left|V_{O V}\right|}=\frac{2 \times 0.267}{0.2}=2.67 \mathrm{~mA} / \mathrm{V}$$
(f)
  
Figure 7.3.2
Refer to Fig. 7.3.2.
$$\begin{aligned}
V_{D} & =V_{D D}-I_{D} R_{D} \
& =1.8-0.267 \times 5=0.465 \mathrm{~V} \
A_{v} & =-g_{m} R_{D}=-2.67 \times 5=-13.35 \mathrm{~V} / \mathrm{V}
\end{aligned}$$
$(\mathrm{g})$
$$\begin{aligned}
V_{A} & =V_{A}^{\prime} \times L \
& =10 \times 0.36=3.6 \mathrm{~V} \
r_{O} & =\frac{V_{A}}{I_{D}}=\frac{3.6}{0.267}=13.5 \mathrm{k} \Omega \
A_{v} & =-g_{m}\left(R_{D} \| r_{O}\right) \
& =-2.67(5 \| 13.5) \
& =-9.74 \mathrm{~V} / \mathrm{V}
\end{aligned}$$

Question 4

Figure 7.4.1
The MOSFET in the circuit of Fig. 7.4.1 has $\mu_{n} C_{o x}(W / L)=4 \mathrm{~mA} / \mathrm{V}^{2}$.
(a) Find the value of $I$ that causes the MOSFET to operate in saturation with an overdrive voltage of $0.25 \mathrm{~V}$.
(b) What value of $R_{D}$ results in $V_{D}=0 \mathrm{~V}$ ?
(c) Find the value of $g_{m}$.
(d) Find the value of $r_{o}$ given that $V_{A}=25 \mathrm{~V}$.
(e) If $R_{\text {in }}$ is to be $1 \mathrm{M} \Omega$, find the value that $R_{G}$ must have. (f) For $R_{\text {sig }}=1 \mathrm{M} \Omega$ and $R_{L}=40 \mathrm{k} \Omega$, find the value of the overall voltage gain $v_{o} / v_{\text {sig }}$.
(g) What does the voltage gain become if $C_{S}$ is removed?

Accepted Answer

The answer of

Figure 7.4.1
The MOSFET in the circuit...

Question 5

Figure 7.5.1 (refer to Figure below)

shows a capacitively coupled amplifier. In the following, assume operation at midband frequencies where the coupling and bypass capacitors behave as short circuits. The BJT has $\beta=99$ and the Early effect can be neglected.
(a) If the de voltage at the base is to be $5 \mathrm{~V}$ and the emitter current $1 \mathrm{~mA}$, find the required value of $\left(R_{E 1}+R_{E 2}\right)$. Assume $V_{B E}=0.7 \mathrm{~V}$.
(b) If the input resistance at the base, $R_{i b}$, is to be $10 \mathrm{k} \Omega$, find the required value of $R_{E 1}$ and hence the value of $R_{E 2}$.
(c) If the dc current in $R_{B 2}$ is to be $0.1 \mathrm{~mA}$, find the values of $R_{B 1}$ and $R_{B 2}$.
(d) Find the value of $R_{C}$ that results in a de voltage of $+6 \mathrm{~V}$ at the collector.
(e) Find the input resistance $R_{\text {in }}$ and the value of $v_{b} / v_{\text {sig. }}$.
(f) Find the value of $v_{o} / v_{b}$.
(g) Find the value of the overall voltage gain $v_{o} / v_{\text {sig }}$.
(h) If the peak amplitude of the signal between base and emitter $\left(v_{\pi}\right)$ is to be limited to $5 \mathrm{mV}$, what are the corresponding amplitudes of $v_{b}, v_{\mathrm{sig}}$, and $v_{o}$ ?

Accepted Answer

The answer of Figure 7.5.1 (refer to Figure below)
 ...

Question 6

Figure 7.6.1
(a) Perform a dc bias design for the amplifier in Fig. 7.6.1. For this purpose, assume $\beta$ is very high and $V_{B E}=0.7 \mathrm{~V}$ and neglect the Early effect. Design to obtain a dc base voltage of $V_{C C} / 3$, a dc emitter current of $1 \mathrm{~mA}$, and a dc voltage at the collector that allows for $\pm 1-\mathrm{V}$ signal swing at the collector with the minimum collector voltage no lower than $V_{B}$. Use a de current in the base voltage divider of $I_{E} / 10$. What values are required for $R_{B 1}, R_{B 2}, R_{E}$, and $R_{C}$ ?
(b) If the transistor has $\beta=100$, find the actual values obtained for $I_{E}, I_{C}, V_{B}$, and $V_{C}$.
(c) What are the values of $g_{m}, r_{e}$, and $r_{\pi}$ at the dc bias point.
(d) Assuming very large coupling and bypass capacitors, find the values of $R_{E 1}$ and $R_{E 2}$ that result in $R_{\text {in }}=10 \mathrm{k} \Omega$.
(e) Find the overall voltage gain $G_{v}=v_{o} / v_{\text {sig }}$.
(f) For $v_{o}$, a sine wave with a $1-\mathrm{V}$ peak amplitude, what is the peak amplitude required of the sine wave $v_{b e}$ ? If this value is greater than $5 \mathrm{mV}$, reduce $v_{\text {sig }}$ to limit the peak amplitude of $v_{b e}$ to $5 \mathrm{mV}$. What is the resulting output voltage in this case?

Accepted Answer

The answer of

Figure 7.6.1
(a) Perform a dc bias...

Question 7

The transistor in the emitter follower of Fig. 7.7.1 (refer to Figure below)

Figure 7.7.1
 has $\beta=100$. Assume $V_{B E}=0.7 \mathrm{~V}$ and neglect the Early effect.
(a) Find the dc emitter current $I_{E}$.
(b) Find the value of the emitter resistance $r_{e}$.
(c) Find the input resistance $R_{\text {in }}$.
(d) Find the voltage gain from signal source to the transistor base, $v_{b} / v_{\text {sig }}$.
(e) Find the voltage gain from transistor base to the output, $v_{o} / v_{b}$.
(f) Find the overall voltage gain, $v_{o} / v_{\text {sig }}$.
(g) Find the output resistance $R_{\text {out }}$.

Accepted Answer

The answer of The transistor in the emitter follower of...

Question 8

Figure 7.8.1
The transistors in the amplifier shown in Fig. 7.8.1
have $\beta=100, V_{B E}=0.7 \mathrm{~V}$, and negligible Early effect.
(a) Design the circuit to obtain the following dc operating parameters: $V_{B 1}=+3 \mathrm{~V}, I_{E 1}=1 \mathrm{~mA}$, $V_{E 2}=+4 \mathrm{~V}$, and $I_{E 2}=4 \mathrm{~mA}$. Use $I=0.1 \mathrm{~mA}$. Find the values of $R_{1}, R_{2}, R_{3},\left(R_{4}+R_{5}\right)$, and $R_{6}$. (b) Find the value of $R_{4}$ (and hence $R_{5}$ ) that results in $R_{\text {in }}=10 \mathrm{k} \Omega$.
(c) Find $R_{i 2}$.
(d) Find the voltage gain $v_{c 1} / v_{i}$.
(e) Find the voltage gain $v_{O} / v_{c 1}$.
(f) Find the overall voltage gain $v_{o} / v_{i}$.
(g) Find the output resistance $R_{\text {out }}$.
(h) In order to minimize nonlinear distortion, it is required to keep the maximum signal across the base-emitter junction of each of $Q_{1}$ and $Q_{2}$ to $5 \mathrm{mV}$. Under this constraint, what is the maximum peak-to-peak sine wave signal that can be obtained at the output?

Accepted Answer

The answer of  
Figure 7.8.1
The transistors in the amplifier...

Quiz 3: Transistor Amplifiers