Question 1

To satisfy the requirements of handheld devices, the classic microprocessor is giving way to the _________ , where not just the CPUs and caches are on the same chip, but also many of the other components of the system, such as DSPs, GPUs, I/O devices and main memory.

Accepted Answer

The answer of To satisfy the requirements of handheld devices,...

Question 2

External, nonvolatile memory is also referred to as __________ or auxiliary memory.

Accepted Answer

The answer of External, nonvolatile memory is also referred to...

Question 3

A __________ computer combines two or more processors on a single piece of silicon.

Accepted Answer

The answer of A __________ computer combines two or more...

Question 4

When an external device is ready to accept more data from the processor, the I/O module for that external device sends an __________ signal to the processor.

Accepted Answer

The answer of When an external device is ready to...

Question 5

The invention of the _________ was the hardware revolution that brought about desktop and handheld computing.

Accepted Answer

The answer of The invention of the _________ was the...

Question 6

The _________ chooses which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks.
A) memory controller
B) mapping function
C) write policy
D) replacement algorithm

Accepted Answer

The replacement algorithm chooses which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks. The other choices (A, B, and C) are important in the caching process but do not specifically pertain to the replacement of a block in the cache.

Question 7

The processing required for a single instruction is called a(n) __________ cycle.

Accepted Answer

The answer of The processing required for a single instruction...

Question 8

The __________ is a point-to-point link electrical interconnect specification that enables high-speed communications among connected processor chips.
A) QPI
B) DDR3
C) LRUA
D) ISR

Accepted Answer

QPI stands for QuickPath Interconnect, which is a point-to-point link electrical interconnect specification used for high-speed communication among connected processor chips. It was developed by Intel and is commonly used in their processors. Option B) DDR3 is a type of memory specification and not related to interconnects. Option C) LRUA and Option D) ISR are not commonly used interconnect specifications.

Question 9

In a uniprocessor system, multiprogramming increases processor efficiency by:
A) Taking advantage of time wasted by long wait interrupt handling
B) Disabling all interrupts except those of highest priority
C) Eliminating all idle processor cycles
D) Increasing processor speed

Accepted Answer

With multiprogramming, multiple processes are loaded into the memory and whenever one process is waiting for an I/O operation or for any other reason, the processor can switch to another ready process. This way, the processor can utilize the time that would otherwise be wasted due to long wait interrupt handling, thus increasing efficiency. Disabling interrupts (B) may affect the responsiveness of the system and eliminating idle processor cycles (C) is not possible as there will always be some idle time due to I/O operations or other external factors. Increasing processor speed (D) may help, but it is not the primary benefit of multiprogramming.

Question 10

The fetched instruction is loaded into the __________ .

Accepted Answer

The answer of The fetched instruction is loaded into the...

Question 11

One mechanism Intel uses to make its caches more effective is __________ , in which the hardware examines memory access patterns and attempts to fill the caches speculatively with data that is likely to be requested soon.
A) mapping
B) handling
C) interconnecting
D) prefetching

Accepted Answer

The mechanism described in the sentence is prefetching, which involves the hardware predicting and filling the caches with data that is likely to be needed soon based on memory access patterns.

Question 12

When an external device becomes ready to be serviced by the processor the device sends a(n) _________ signal to the processor.
A) access
B) halt
C) handler
D) interrupt

Accepted Answer

When an external device becomes ready to be serviced by the processor, it interrupts the processor by sending an interrupt signal. This prompts the processor to stop its current task and switch its attention to the external device that needs attention. Therefore, the best choice is D - interrupt. The other options, including access, halt, and handler, do not accurately describe the signal sent by the external device to the processor.

Question 13

In a _________ multiprocessor all processors can perform the same functions so the failure of a single processor does not halt the machine.

Accepted Answer

The answer of In a _________ multiprocessor all processors can...

Question 14

When a new block of data is read into the cache the __________ determines which cache location the block will occupy.

Accepted Answer

The answer of When a new block of data is...

Question 15

The two basic types of processor registers are:
A) User-visible and user-invisible registers
B) Control and user-invisible registers
C) Control and Status registers
D) User-visible and Control/Status registers

Accepted Answer

The two basic types of processor registers are user-visible and control/status registers. User-visible registers are used for performing arithmetic and logical operations and for storing intermediate results. Control/status registers, on the other hand, provide control and status information about the processor, such as the mode of operation, interrupt handling, and condition codes. Therefore, option D is the correct answer.

Question 16

Small, fast memory located between the processor and main memory is called:
A) Block memory
B) Cache memory
C) Direct memory
D) WORM memory

Accepted Answer

Cache memory is a small and fast memory that stores the most frequently accessed data and instructions from the main memory. It is located between the processor and main memory to improve the overall system performance. Block memory, direct memory, and WORM memory are not similar to cache memory and do not perform the same function.

Question 17

The unit of data exchanged between cache and main memory is __________ .
A) block size
B) map size
C) cache size
D) slot size

Accepted Answer

The unit of data exchanged between cache and main memory is the block size. This is because cache and main memory communicate by transferring data in fixed-size blocks, and the block size is the unit of data transferred between them. The other options (map size, cache size, slot size) are not related to the data exchanged between cache and main memory.

Question 18

The __________ is a device for staging the movement of data between main memory and processor registers to improve performance and is not usually visible to the programmer or processor.

Accepted Answer

The answer of The __________ is a device for staging...

Question 19

A __________ organization has a number of potential advantages over a uniprocessor organization including performance, availability, incremental growth, and scaling.
A) temporal locality
B) symmetric multiprocessor
C) direct memory access
D) processor status word

Accepted Answer

A symmetric multiprocessor organization allows for the use of multiple processors to share the workload, resulting in improved performance, availability, and the ability to incrementally grow and scale the system. Direct memory access and processor status words are related to specific hardware components and do not provide the same advantages as a symmetric multiprocessor organization. Temporal locality refers to the concept of data being accessed frequently and can contribute to improved performance, but is not a type of organization.

Question 20

__________ is more efficient than interrupt-driven or programmed I/O for a multiple-word I/O transfer.
A) Spatial locality
B) Direct memory access
C) Stack access
D) Temporal locality

Accepted Answer

Direct memory access (DMA) is more efficient than interrupt-driven or programmed I/O for a multiple-word I/O transfer because it allows the transfer of data between peripherals and memory without the involvement of the CPU. DMA transfers a block of data directly from the I/O device to memory, or vice versa, without requiring the CPU to be involved in every transfer. This reduces the overhead associated with managing I/O and frees up the CPU to perform other tasks, resulting in better system performance. The other options relate to memory access patterns and are not directly relevant to I/O transfer efficiency.

Quiz 1: Computer Systems Overview

To satisfy the requirements of handheld devices, the classic microprocessor is giving way to the _________ , where not just the CPUs and caches are on the same chip, but also many of the other components of the system, such as DSPs, GPUs, I/O devices and main memory.

External, nonvolatile memory is also referred to as __________ or auxiliary memory.

A __________ computer combines two or more processors on a single piece of silicon.

When an external device is ready to accept more data from the processor, the I/O module for that external device sends an __________ signal to the processor.

The invention of the _________ was the hardware revolution that brought about desktop and handheld computing.

The _________ chooses which block to replace when a new block is to be loaded into the cache and the cache already has all slots filled with other blocks.

The processing required for a single instruction is called a(n) __________ cycle.

The __________ is a point-to-point link electrical interconnect specification that enables high-speed communications among connected processor chips.

In a uniprocessor system, multiprogramming increases processor efficiency by:

The fetched instruction is loaded into the __________ .

One mechanism Intel uses to make its caches more effective is __________ , in which the hardware examines memory access patterns and attempts to fill the caches speculatively with data that is likely to be requested soon.

When an external device becomes ready to be serviced by the processor the device sends a(n) _________ signal to the processor.

In a _________ multiprocessor all processors can perform the same functions so the failure of a single processor does not halt the machine.

When a new block of data is read into the cache the __________ determines which cache location the block will occupy.

The two basic types of processor registers are:

Small, fast memory located between the processor and main memory is called:

The unit of data exchanged between cache and main memory is __________ .

The __________ is a device for staging the movement of data between main memory and processor registers to improve performance and is not usually visible to the programmer or processor.

A __________ organization has a number of potential advantages over a uniprocessor organization including performance, availability, incremental growth, and scaling.

__________ is more efficient than interrupt-driven or programmed I/O for a multiple-word I/O transfer.