Figure 941
for the Circuit Shown in Fig $V_{B E}=0.7 \mathrm{~V}$

Figure 9.4.1
For the circuit shown in Fig. 9.4.1, neglect base currents in dc calculations and assume that for each transistor $V_{B E}=0.7 \mathrm{~V}$ . Transistors $Q_{1}$ and $Q_{2}$ are perfectly matched. Transistor $Q_{3}$ has twice the emitter-base junction area of $Q_{4}$ .
(a) For $v_{B 1}=v_{B 2}=0 \mathrm{~V}$ , design the circuit to establish a dc bias current of $0.1 \mathrm{~mA}$ in the collector of each of $Q_{1}$ and $Q_{2}$ and a dc voltage of $+1 \mathrm{~V}$ at the collector of each of $Q_{1}$ and $Q_{2}$ . Specify the values required for $R, R_{1}$ , and $R_{2}$ .
(b) For $v_{B 1}=v_{i d} / 2$ and $v_{B 2}=-v_{i d} / 2$ , determine the differential small-signal voltage gain $v_{o d} / v_{i d}$ . Ignore the Early effect. If $\beta_{1}=\beta_{2}=100$ , what is the differential input resistance of the differential amplifier $Q_{1}-Q_{2}$ ?
(c) If $Q_{3}$ has an Early voltage of $100 \mathrm{~V}$ , find its output resistance and use this result to determine the common-mode gain of the differential amplifier $v_{o d} / v_{i c m}$ , where $v_{B 1}=v_{B 2}=v_{i c m}$ and assuming that each of $R_{1}$ and $R_{2}$ is accurate to within $\pm 1 \%$ . What is the resulting CMRR in decibels?