Figure 991
the Two-Stage CMOS Op Amp Shown in Fig $0.18-\mu \mathrm{m}$

Figure 9.9.1
The two-stage CMOS op amp shown in Fig. 9.9.1 is fabricated in a $0.18-\mu \mathrm{m}$ technology having $k_{n}^{\prime}=$ $4 k_{p}^{\prime}=400 \mu \mathrm{A} / \mathrm{V}^{2}$ , and $V_{t n}=-V_{t p}=0.4 \mathrm{~V}$ .
(a) With $A$ and $B$ grounded, perform a de design that will result in each of $Q_{1}, Q_{2}, Q_{3}$ , and $Q_{4}$ conducting a drain current of $100 \mu \mathrm{A}$ , and each of $Q_{5}, Q_{6}$ , and $Q_{7}$ conducting a drain current of $200 \mu \mathrm{A}$ . Design so that all transistors operate at a $0.2-\mathrm{V}$ overdrive voltage. Neglect the Early effect. Specify the $W / L$ ratio required for each MOSFET.
Present your results in a table. What is the dc voltage at the output (ideally)?
(b) Find the input common-mode range.
(c) Find the allowable range of the output voltage.
(d) With $v_{A}=v_{i d} / 2$ and $v_{B}=-v_{i d} / 2$ , find the voltage gain $v_{O} / v_{i d}$ . Assume that the Early voltage is $\left|V_{A}\right|=5 \mathrm{~V}$ .