A $0.18-\mu \mathrm{m}$ CMOS technology is specified to have $\mu_{n}=450 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, \mu_{p}=100 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, C_{o x}=$ $8.6 \mathrm{fF} / \mu \mathrm{m}^{2}, V_{t n}=-V_{t p}=0.5 \mathrm{~V}$, and dc power supply of $1.8 \mathrm{~V}$.
(a) Find the transconductance parameters $k_{n}^{\prime}$ and $k_{p}^{\prime}$ expressed in $\mu \mathrm{A} / \mathrm{V}^{2}$.
(b) Find the $W / L$ ratios of matched NMOS and PMOS transistors that exhibit resistance $r_{D S}$ of $250 \Omega$ when operated in the triode region with an overdrive voltage of $0.3 \mathrm{~V}$. If twice-theminimum channel length is used, specify the width of the NMOS transistor and the PMOS transistor.
(c) If the devices in (b) are operated in saturation with $\left|V_{O V}\right|=0.2 \mathrm{~V}$, what drain current results? If for each transistor the source is connected to ground, what should the gate voltages be? In each case, specify the range of voltages permitted at the drain for saturation-mode operation to be maintained.
(d) If the drain currents in (c) are to be reduced by a factor of 4 , what should the overdrive voltage be? If instead of changing $\left|V_{O V}\right|$, the IC designer redesigns the widths of the transistors, what $W$ values would be required?
(e) If the devices described in (b) above are operated in saturation with $\left|V_{O V}\right|=0.2 \mathrm{~V}$, find the resulting value of $g_{m}$.
(f) If an NMOS transistor as in (e) above is connected as a common-source amplifier with $R_{D}=$ $5 \mathrm{k} \Omega$ and $V_{D D}=1.8 \mathrm{~V}$, what dc voltage would appear at the drain? What small-signal voltage gain $A_{v}$ would be obtained?
(g) Recalculate the voltage gain in (f) taking into account channel-length modulation. Assume the
Early voltage for the process technology is specified as $10 \mathrm{~V} / \mu \mathrm{m}$.

Question

Quizplus · Accepted Answer

The Answer is (a)

\begin{aligned}k_{n}^{\prime} & =\mu_{n} C_{o x} \& =450 \frac{\mathrm{cm}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \& =450 imes 10^{8} \frac{\mu \mathrm{m}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \& =387 imes 10^{-6} \frac{\mathrm{F}}{\mathrm{V} \cdot \mathrm{s}} \& =387 \mu \mathrm{A} / \mathrm{V}^{2} \k_{p}^{\prime} & =k_{n}^{\prime} imes \frac{\mu_{p}}{\mu_{n}}=387 imes \frac{100}{450} \& =86 \mu \mathrm{A} / \mathrm{V}^{2}\end{aligned}

(b) For an NMOS transistor operating in a triode region,

\begin{aligned}r_{D S} & =\frac{1}{k_{n}^{\prime}(W / L)_{N} V_{O V}} \250 & =\frac{1}{387 imes 10^{-6} imes(W / L)_{N} imes 0.3} \\Rightarrow(W / L)_{N} & =34.5\end{aligned}

For a matched PMOS transistor,

\begin{aligned}(W / L)_{P} & =(W / L)_{N} imes \frac{k_{n}^{\prime}}{k_{p}^{\prime}} \& =34.5 imes \frac{387}{86}=155\end{aligned}

Thus,

\begin{aligned}L & =2 L_{\min }=2 imes 0.18=0.36 \mu \mathrm{m} \W_{N} & =34.5 imes 0.36=12.4 \mu \mathrm{m} \W_{P} & =155 imes 0.36=55.8 \mu \mathrm{m}\end{aligned}

(c)

\begin{aligned}I_{D P} & =I_{D N}=\frac{1}{2} k_{n}^{\prime}(W / L)_{N}\left|V_{O V} ight|^{2} \& =\frac{1}{2} imes 387 imes 34.5 imes 0.2^{2} \& =267 \mu \mathrm{A}\end{aligned}

For the NMOS transistor,

V_{G}=V_{G S}=V_{t n}+V_{O V}=0.5+0.2=0.7 \mathrm{~V}

For the PMOS transistor,
$(a) \begin{aligned} k_{n}^{\prime} & =\mu_{n} C_{o x} \ & =450 \frac{\mathrm{cm}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \ & =450 imes 10^{8} \frac{\mu \mathrm{m}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \ & =387 imes 10^{-6} \frac{\mathrm{F}}{\mathrm{V} \cdot \mathrm{s}} \ & =387 \mu \mathrm{A} / \mathrm{V}^{2} \ k_{p}^{\prime} & =k_{n}^{\prime} imes \frac{\mu_{p}}{\mu_{n}}=387 imes \frac{100}{450} \ & =86 \mu \mathrm{A} / \mathrm{V}^{2} \end{aligned} (b) For an NMOS transistor operating in a triode region, \begin{aligned} r_{D S} & =\frac{1}{k_{n}^{\prime}(W / L)_{N} V_{O V}} \ 250 & =\frac{1}{387 imes 10^{-6} imes(W / L)_{N} imes 0.3} \ \Rightarrow(W / L)_{N} & =34.5 \end{aligned} For a matched PMOS transistor, \begin{aligned} (W / L)_{P} & =(W / L)_{N} imes \frac{k_{n}^{\prime}}{k_{p}^{\prime}} \ & =34.5 imes \frac{387}{86}=155 \end{aligned} Thus, \begin{aligned} L & =2 L_{\min }=2 imes 0.18=0.36 \mu \mathrm{m} \ W_{N} & =34.5 imes 0.36=12.4 \mu \mathrm{m} \ W_{P} & =155 imes 0.36=55.8 \mu \mathrm{m} \end{aligned} (c) \begin{aligned} I_{D P} & =I_{D N}=\frac{1}{2} k_{n}^{\prime}(W / L)_{N}\left|V_{O V} ight|^{2} \ & =\frac{1}{2} imes 387 imes 34.5 imes 0.2^{2} \ & =267 \mu \mathrm{A} \end{aligned} For the NMOS transistor, V_{G}=V_{G S}=V_{t n}+V_{O V}=0.5+0.2=0.7 \mathrm{~V} For the PMOS transistor, Figure 7.3.1 From Fig. 7.3.1, we see that for the NMOS transistor to operate in saturation, V_{D} \geq V_{O V} that is, V_{D} \geq 0.2 \mathrm{~V} For the PMOS transistor to operate in saturation, V_{D} \leq-\left|V_{O V} ight| that is, V_{D} \leq-0.2 \mathrm{~V} (d) Since I_{D} is proportional to \left|V_{O V} ight|^{2} , the drain current can be reduced by a factor of 4 by reducing \left|V_{O V} ight| by a factor of 2 , that is, to 0.1 \mathrm{~V} . Alternatively, \left|V_{O V} ight| can be kept constant and W reduced by a factor of 4 , resulting in W_{N}=\frac{34.5}{4}=8.63 \mu \mathrm{m} and W_{P}=\frac{155}{4}=38.8 \mu \mathrm{m} (e) g_{m}=\frac{2 I_{D}}{\left|V_{O V} ight|}=\frac{2 imes 0.267}{0.2}=2.67 \mathrm{~mA} / \mathrm{V} (f) Figure 7.3.2 Refer to Fig. 7.3.2. \begin{aligned} V_{D} & =V_{D D}-I_{D} R_{D} \ & =1.8-0.267 imes 5=0.465 \mathrm{~V} \ A_{v} & =-g_{m} R_{D}=-2.67 imes 5=-13.35 \mathrm{~V} / \mathrm{V} \end{aligned} (\mathrm{g}) \begin{aligned} V_{A} & =V_{A}^{\prime} imes L \ & =10 imes 0.36=3.6 \mathrm{~V} \ r_{O} & =\frac{V_{A}}{I_{D}}=\frac{3.6}{0.267}=13.5 \mathrm{k} \Omega \ A_{v} & =-g_{m}\left(R_{D} \| r_{O} ight) \ & =-2.67(5 \| 13.5) \ & =-9.74 \mathrm{~V} / \mathrm{V} \end{aligned}$
Figure 7.3.1
From Fig. 7.3.1, we see that for the NMOS transistor to operate in saturation,

V_{D} \geq V_{O V}

that is,

V_{D} \geq 0.2 \mathrm{~V}

For the PMOS transistor to operate in saturation,

V_{D} \leq-\left|V_{O V} ight|

that is,

V_{D} \leq-0.2 \mathrm{~V}

(d) Since

I_{D}

is proportional to

\left|V_{O V} ight|^{2}

, the drain current can be reduced by a factor of 4 by reducing

\left|V_{O V} ight|

by a factor of 2 , that is, to

0.1 \mathrm{~V}

. Alternatively,

\left|V_{O V} ight|

can be kept constant and

W

reduced by a factor of 4 , resulting in

W_{N}=\frac{34.5}{4}=8.63 \mu \mathrm{m}

and

W_{P}=\frac{155}{4}=38.8 \mu \mathrm{m}

(e)

g_{m}=\frac{2 I_{D}}{\left|V_{O V} ight|}=\frac{2 imes 0.267}{0.2}=2.67 \mathrm{~mA} / \mathrm{V}

(f)
$(a) \begin{aligned} k_{n}^{\prime} & =\mu_{n} C_{o x} \ & =450 \frac{\mathrm{cm}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \ & =450 imes 10^{8} \frac{\mu \mathrm{m}^{2}}{\mathrm{~V} \cdot \mathrm{s}} imes 8.6 imes 10^{-15} \frac{\mathrm{F}}{\mu \mathrm{m}^{2}} \ & =387 imes 10^{-6} \frac{\mathrm{F}}{\mathrm{V} \cdot \mathrm{s}} \ & =387 \mu \mathrm{A} / \mathrm{V}^{2} \ k_{p}^{\prime} & =k_{n}^{\prime} imes \frac{\mu_{p}}{\mu_{n}}=387 imes \frac{100}{450} \ & =86 \mu \mathrm{A} / \mathrm{V}^{2} \end{aligned} (b) For an NMOS transistor operating in a triode region, \begin{aligned} r_{D S} & =\frac{1}{k_{n}^{\prime}(W / L)_{N} V_{O V}} \ 250 & =\frac{1}{387 imes 10^{-6} imes(W / L)_{N} imes 0.3} \ \Rightarrow(W / L)_{N} & =34.5 \end{aligned} For a matched PMOS transistor, \begin{aligned} (W / L)_{P} & =(W / L)_{N} imes \frac{k_{n}^{\prime}}{k_{p}^{\prime}} \ & =34.5 imes \frac{387}{86}=155 \end{aligned} Thus, \begin{aligned} L & =2 L_{\min }=2 imes 0.18=0.36 \mu \mathrm{m} \ W_{N} & =34.5 imes 0.36=12.4 \mu \mathrm{m} \ W_{P} & =155 imes 0.36=55.8 \mu \mathrm{m} \end{aligned} (c) \begin{aligned} I_{D P} & =I_{D N}=\frac{1}{2} k_{n}^{\prime}(W / L)_{N}\left|V_{O V} ight|^{2} \ & =\frac{1}{2} imes 387 imes 34.5 imes 0.2^{2} \ & =267 \mu \mathrm{A} \end{aligned} For the NMOS transistor, V_{G}=V_{G S}=V_{t n}+V_{O V}=0.5+0.2=0.7 \mathrm{~V} For the PMOS transistor, Figure 7.3.1 From Fig. 7.3.1, we see that for the NMOS transistor to operate in saturation, V_{D} \geq V_{O V} that is, V_{D} \geq 0.2 \mathrm{~V} For the PMOS transistor to operate in saturation, V_{D} \leq-\left|V_{O V} ight| that is, V_{D} \leq-0.2 \mathrm{~V} (d) Since I_{D} is proportional to \left|V_{O V} ight|^{2} , the drain current can be reduced by a factor of 4 by reducing \left|V_{O V} ight| by a factor of 2 , that is, to 0.1 \mathrm{~V} . Alternatively, \left|V_{O V} ight| can be kept constant and W reduced by a factor of 4 , resulting in W_{N}=\frac{34.5}{4}=8.63 \mu \mathrm{m} and W_{P}=\frac{155}{4}=38.8 \mu \mathrm{m} (e) g_{m}=\frac{2 I_{D}}{\left|V_{O V} ight|}=\frac{2 imes 0.267}{0.2}=2.67 \mathrm{~mA} / \mathrm{V} (f) Figure 7.3.2 Refer to Fig. 7.3.2. \begin{aligned} V_{D} & =V_{D D}-I_{D} R_{D} \ & =1.8-0.267 imes 5=0.465 \mathrm{~V} \ A_{v} & =-g_{m} R_{D}=-2.67 imes 5=-13.35 \mathrm{~V} / \mathrm{V} \end{aligned} (\mathrm{g}) \begin{aligned} V_{A} & =V_{A}^{\prime} imes L \ & =10 imes 0.36=3.6 \mathrm{~V} \ r_{O} & =\frac{V_{A}}{I_{D}}=\frac{3.6}{0.267}=13.5 \mathrm{k} \Omega \ A_{v} & =-g_{m}\left(R_{D} \| r_{O} ight) \ & =-2.67(5 \| 13.5) \ & =-9.74 \mathrm{~V} / \mathrm{V} \end{aligned}$
Figure 7.3.2
Refer to Fig. 7.3.2.

\begin{aligned}V_{D} & =V_{D D}-I_{D} R_{D} \& =1.8-0.267 imes 5=0.465 \mathrm{~V} \A_{v} & =-g_{m} R_{D}=-2.67 imes 5=-13.35 \mathrm{~V} / \mathrm{V}\end{aligned}

(\mathrm{g})

\begin{aligned}V_{A} & =V_{A}^{\prime} imes L \& =10 imes 0.36=3.6 \mathrm{~V} \r_{O} & =\frac{V_{A}}{I_{D}}=\frac{3.6}{0.267}=13.5 \mathrm{k} \Omega \A_{v} & =-g_{m}\left(R_{D} \| r_{O} ight) \& =-2.67(5 \| 13.5) \& =-9.74 \mathrm{~V} / \mathrm{V}\end{aligned}

A 0.18−μm0.18-\mu \mathrm{m}0.18−μm CMOS Technology Is Specified to Have μn=450 cm2/V⋅s,μp=100 cm2/V⋅s,Cox=\mu_{n}=450 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, \mu_{p}=100 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, C_{o x}=μn​=450 cm2/V⋅s,μp​=100 cm2/V⋅s,Cox​=

A $0.18-\mu \mathrm{m}$ CMOS Technology Is Specified to Have $\mu_{n}=450 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, \mu_{p}=100 \mathrm{~cm}^{2} / \mathrm{V} \cdot \mathrm{s}, C_{o x}=$