Figure 761
(A) Perform a Dc Bias Design for the Amplifier

Figure 7.6.1
(a) Perform a dc bias design for the amplifier in Fig. 7.6.1. For this purpose, assume $\beta$ is very high and $V_{B E}=0.7 \mathrm{~V}$ and neglect the Early effect. Design to obtain a dc base voltage of $V_{C C} / 3$ , a dc emitter current of $1 \mathrm{~mA}$ , and a dc voltage at the collector that allows for $\pm 1-\mathrm{V}$ signal swing at the collector with the minimum collector voltage no lower than $V_{B}$ . Use a de current in the base voltage divider of $I_{E} / 10$ . What values are required for $R_{B 1}, R_{B 2}, R_{E}$ , and $R_{C}$ ?
(b) If the transistor has $\beta=100$ , find the actual values obtained for $I_{E}, I_{C}, V_{B}$ , and $V_{C}$ .
(c) What are the values of $g_{m}, r_{e}$ , and $r_{\pi}$ at the dc bias point.
(d) Assuming very large coupling and bypass capacitors, find the values of $R_{E 1}$ and $R_{E 2}$ that result in $R_{\text {in }}=10 \mathrm{k} \Omega$ .
(e) Find the overall voltage gain $G_{v}=v_{o} / v_{\text {sig }}$ .
(f) For $v_{o}$ , a sine wave with a $1-\mathrm{V}$ peak amplitude, what is the peak amplitude required of the sine wave $v_{b e}$ ? If this value is greater than $5 \mathrm{mV}$ , reduce $v_{\text {sig }}$ to limit the peak amplitude of $v_{b e}$ to $5 \mathrm{mV}$ . What is the resulting output voltage in this case?